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Visitor
Visitor
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Registered: ‎03-19-2020

Inspecting full value of a signal

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I am working on a project that includes large bit vectors with > 10k bits. I am looking for a way to see the entire value of the vector in the simulation to be able to verify whether it has the correct value or not. Right now the simulation seems to only show the first 256 hex signs, so the first 1024 bits. 

Screen1.png

As you can see in the photo the value for test is longer than it is currently depicted. 

Does anyone know of a way to change this?

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-16-2008

回复: Inspecting full value of a signal

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Try to change the array display limit and launch a new simulation.

set_property xsim.array_display_limit size [current_project]

Replace size with your number. By default, it's 1024.

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Scholar
Scholar
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Registered: ‎08-01-2012

Re: Inspecting full value of a signal

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Why such a large array?

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Teacher
Teacher
427 Views
Registered: ‎07-09-2009

Re: Inspecting full value of a signal

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Have you tried moving the vertical edge of the signals to the right to make the signals window bigger.

BTW: I have never heard of such a massive vector,
thats amazing,
whats it used for ?
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Visitor
Visitor
416 Views
Registered: ‎03-19-2020

Re: Inspecting full value of a signal

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Yes I tried this, I can still only see up to 256 Hex signs.

I am trying to implement an encryption scheme that makes use of a pseudorandom matrix. Each of the rows consists of 16 bit values with >640 values per row, and the rows are generated by hashing a row index||seed, therefore the large vector.

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Scholar
Scholar
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Registered: ‎08-01-2012

Re: Inspecting full value of a signal

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Why cant you just create an array of 16 bit values?

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Teacher
Teacher
371 Views
Registered: ‎07-09-2009

Re: Inspecting full value of a signal

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VHDL et all supports multi dimensional structures,

https://www.ics.uci.edu/~jmoorkan/vhdlref/arrays.html

https://www.nandland.com/vhdl/examples/example-array-type-vhdl.html

Its no answer to what seems like a bug ,
but it may be explains why its not been seen before
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Xilinx Employee
Xilinx Employee
320 Views
Registered: ‎07-16-2008

回复: Inspecting full value of a signal

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Try to change the array display limit and launch a new simulation.

set_property xsim.array_display_limit size [current_project]

Replace size with your number. By default, it's 1024.

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

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Visitor
Visitor
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Registered: ‎03-19-2020

回复: Inspecting full value of a signal

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Yes, that's what I was looking for, thank you very much!

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