08-25-2012 04:32 AM
I've got problem with simulating my design. It's modified version of PCIE SG DMA project from opencores.
Project consists of VHDL desing and Verilog testbench.
During simulation, *all* FIFO and BRAM cores have undefined outputs (I don't test PCIe core).
Hovewer, simulation script provided with FIFO core works OK (I mean ipcore_dir/fifo/simulation/...).
Additionaly I get some warnings in console when opening project, e.g.:
WARNING:ProjectMgmt - Duplicate Design Unit 'sfifo_15x128' found in library 'work' WARNING:ProjectMgmt - "/home/adrian/praca/pcie_dma/ipcore_dir/sfifo_15x128.vhd" line 43 (active) WARNING:ProjectMgmt - "/home/adrian/praca/pcie_dma/ipcore_dir/sfifo_15x128_synth.vhd" line 57
and when starting simulation:
WARNING:HDLCompiler:685 - "/home/adrian/praca/pcie_dma/ipcore_dir/sfifo_15x128_synth.vhd" Line 57: Overwriting existing primary unit sfifo_15x128
Cleaning project files or regenerating cores didn't help.
I've got "`timescale 1ns / 1ps" directive in Verilog file and I'm holding reset for 101 ns.
I use ISE 14.2.