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Observer agary
Observer
1,066 Views
Registered: ‎05-17-2018

Is Post-Implementation Timing Simulation result important?

My behavioral, post-synthesis functional, post-synthesis timing and post-implementation functional simulation results are the same and as expected.

But I got very strange post-implementation timing simulation results and every time I make very small changes, I get different results. Now, should I notice this simulation mismatch or is it ignorable? If it is important, then how can I find the cause of the issue?

Thanks.

P.S. My design is almost fully synchronized with just one clock signal.

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7 Replies
Scholar drjohnsmith
Scholar
1,055 Views
Registered: ‎07-09-2009

Re: Is Post-Implementation Timing Simulation result important?

Assuming you have th etimming constraints se tup corret 

   and you pass timming, 

all is ok

Post synth simulation is primarily used to prove that what was synthesised meets the design logical specifications, and the synthesis has not done 'different' to what you expected.

As a yard stick,

   I must have performed many thousand simulation runs on designs over the last 40 years , of which a hand full were post synthesis runs. 

 

BTW: For Vivado, post simulation with timing is broken for VHDL, 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
1,038 Views
Registered: ‎01-22-2015

Re: Is Post-Implementation Timing Simulation result important?

@drjohnsmith

      BTW: For Vivado, post simulation with timing is broken for VHDL,

We now seem to have a workaround to the problem of Post-Implementation Timing Simulation with VHDL. Please see the solution associated with <this> post.

Mark

 

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Observer agary
Observer
1,028 Views
Registered: ‎05-17-2018

Re: Is Post-Implementation Timing Simulation result important?

This is what I've passed to my Main.xdc file:

create_clock -period 10.000 -name s00_axi_aclk -waveform {0.000 5.000} [get_ports s00_axi_aclk]

"Report Clock Networks" says this is the only clock signal I have, and timing report says I have no negative slack at all. So I think it means that I have correct timing constraints. What do you think?

Now you say I should not pay attention to post-implementation timing simulation results, right?

Would you mind tell me more about the second part of your answer? How do you figure out which part of the design needs changes to meet the specs after synthesizing? Do you try to use "Mark for Debugging" directives to check the signals later? I'm asking because my main design works perfectly as I mentioned before (i.e. all simulations has been passed except post-implementation timing), but now after adding a new module to my design (i.e. AXI slave interface), I can pass the behavioral simulation but there are problems with post-synthesis functional simulation.

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939 Views
Registered: ‎01-22-2015

Re: Is Post-Implementation Timing Simulation result important?

@agary

Like drjohnsmith, many of us identify and solve timing analysis problems using only the reports given by timing analysis. However, it seems you are doing some unique and interesting things with timing simulation that I’d like to hear about.

First, a few background questions for you:

  1. What is the part number for the FPGA you are using?
  2. Which programming language (VHDL, Verilog, HLS)?
  3. Which version of Vivado?

     P.S. My design is almost fully synchronized with just one clock signal.
Having a single-clock design is a rare blessing. Please tell me how you bring this clock into the FPGA. Is this clock routed immediately to an MMCM or PLL once it enters the FPGA?

     But I got very strange post-implementation timing simulation results and every time I make very small changes, I get different results.
Please describe this in more detail – maybe with some screen-shots of what you are seeing.

Cheers,
Mark

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Scholar drjohnsmith
Scholar
931 Views
Registered: ‎07-09-2009

Re: Is Post-Implementation Timing Simulation result important?

you say "except post-implementation timing"

that means your design does not work,
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Adventurer
Adventurer
902 Views
Registered: ‎10-04-2018

Re: Is Post-Implementation Timing Simulation result important?

I would recommend just do STA, make sure that no timing violation and forget about post-routed-timing simulaiton for FPGA ( never forget for ASIC).

Than programm your FPGA and see if it works ( mostlly it always works).

 

but if STA does not give errors and FPGA does not work than go back and analyses synthesis results for error/warnings and also use Chipscope to debug.

To my opinion, post pr timing simulation is much time consuming for FPGA designs as moslty FPGA provides many other benefits to debug than post pr simulaiton.

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Scholar richardhead
Scholar
888 Views
Registered: ‎08-01-2012

Re: Is Post-Implementation Timing Simulation result important?

P.S. My design is almost fully synchronized with just one clock signal.

What does this mean? do you have critical signals not safely synchronised? are you relying on netlist simulation to prove behaviour?

12 years in industry. Never run a netlist simulation. Good design practice (synchronise everything unless there is a good reason not to, with well audited design), RTL simulation and STA have worked just fine for me. I'm working with 10G MACs, DDR etc and never had a problem. Well designed RTL testbenches and well focussed chipscope have always fixed the problem (including synth bugs!)

You mention problems with AXI slave interface - are you sure your design meets the AXI specification? the one that usually catches people out is that _ready is allowed to be a reflection of _valid, but it is forbidden for _valid to rely on _ready (to prevent deadlock). Have you tried simulating against an AXI BFM?

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