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Observer abet
Observer
407 Views
Registered: ‎09-03-2018

Is VHDL supported for post-synth timing simulation in free HLS Web Pack? [Vivado 2018.3 - Ubuntu 18.04]

Hi to you all.

I'm new to vivado and I'm doing now my first timing oriented VHDL programming.

As I try to run a post-synthesis timing simulation in Vivado, I got a pop-up (see image) saying tha VHDL is not supported unless my simulator's (Xsim I guess) licence includes it. Now, I downloaded the plain Web Pack. Does this support timing?

Selection_132.png
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10 Replies
Scholar richardhead
Scholar
391 Views
Registered: ‎08-01-2012

Re: Is VHDL supported for post-synth timing simulation in free HLS Web Pack? [Vivado 2018.3]

The warning is because some external tools require a separate (more expensive licence) for mixed language design.

Vivado will only output a timing netlist in verilog, so if you specify VHDL you are likely to have  VHDL testbench and therefore require a mixed language licence.

Vivado does support mixed language simulation.

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Xilinx Employee
Xilinx Employee
376 Views
Registered: ‎07-16-2008

回复: Is VHDL supported for post-synth timing simulation in free HLS Web Pack? [Vivado 2018.3]

Xsim doesn't support timing simulation in VHDL. This has nothing to do with the WebPACK license.

Here's more information from UG900.

IMPORTANT: Timing simulation is supported in Verilog only; there is no VHDL version of the SIMPRIM library.
TIP: If you are a VHDL user, you can run post synthesis and post implementation functional simulation (in which case no standard default format (SDF) annotation is required and the simulation netlist uses the UNISIM library). You can create the netlist using the write_vhdl Tcl command.

The message warns you that if you proceed, a Verilog netlist will be generated for timing simulation. You need to ensure the target simulator has Verilog simulation license, which is not a problem for Xsim.

 

I unzip the project and perform post-synth timing simulation on top of simset 'cmplx'. I could launch the simulation successfully. The 'PATHPULSE' field is set to 50.0. Attached is the SDF generated at my end.

 

I do notice a warning about board_part when opening the project. Other than that, I didn't change any settings.

CRITICAL WARNING: [Board 49-67] The board_part definition was not found for digilentinc.com:nexys4_ddr:part0:1.1. This can happen sometimes when you use custom board part. You can resolve this issue by setting 'board.repoPaths' parameter, pointing to the location of custom board files. Valid board_part values can be retrieved with the 'get_board_parts' Tcl command.

 

What if you change the Simulator Language option from VHDL to Mixed?

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Observer abet
Observer
365 Views
Registered: ‎09-03-2018

回复: Is VHDL supported for post-synth timing simulation in free HLS Web Pack? [Vivado 2018.3]

Hi,

so i tried changing the language but this unfortunately does not help.
I compared the two files with meld and wath i see is that the differences lie in PATHPULSE and IOPATH. Now, I don't understand how the sdf file is built but here i report an example.
As you said

mine:
(PATHPULSE (0,0))
...
      (IOPATH I5 O (0.0:0.0:0.0) (0.0:0.0:0.0))
      (IOPATH I4 O (0.0:0.0:0.0) (0.0:0.0:0.0))
      (IOPATH I3 O (0.0:0.0:0.0) (0.0:0.0:0.0))
      (IOPATH I2 O (0.0:0.0:0.0) (0.0:0.0:0.0))
      (IOPATH I1 O (0.0:0.0:0.0) (0.0:0.0:0.0))
      (IOPATH I0 O (0.0:0.0:0.0) (0.0:0.0:0.0))

yours:
(PATHPULSE (50.0))
...
      (IOPATH I5 O (100.0:124.0:124.0) (100.0:124.0:124.0))
      (IOPATH I4 O (100.0:124.0:124.0) (100.0:124.0:124.0))
      (IOPATH I3 O (100.0:124.0:124.0) (100.0:124.0:124.0))
      (IOPATH I2 O (100.0:124.0:124.0) (100.0:124.0:124.0))
      (IOPATH I1 O (100.0:124.0:124.0) (100.0:124.0:124.0))
      (IOPATH I0 O (100.0:124.0:124.0) (100.0:124.0:124.0))

And this repeats every time pathpuls/iopath are called.

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Observer abet
Observer
364 Views
Registered: ‎09-03-2018

回复: Is VHDL supported for post-synth timing simulation in free HLS Web Pack? [Vivado 2018.3]

Also, is there a way I could use your sdf file preventing the over-write in order to test if this is the main (and only) problem?
Thanks for the help really:)

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Xilinx Employee
Xilinx Employee
344 Views
Registered: ‎07-16-2008

回复: Is VHDL supported for post-synth timing simulation in free HLS Web Pack? [Vivado 2018.3]

Not sure why the auto-generated SDF files are not the same. I have a system edition license, but I wouldn't expect that will make the change.

If you launch simulation from GUI, it will overwrite the SDF file and re-generate a one. You may try to edit the post-synth timing simulation netlist at

<project>.sim/cmplx/synth/timing/cfg_tb_ps_mult_booth_array_cmplx_time_synth.v

Replace the .sdf file in the following line,
initial begin
$sdf_annotate("cfg_tb_ps_mult_booth_array_cmplx_time_synth.sdf",,,,"tool_control");

Of if you copy my .sdf to the same directory to replace the original .sdf file, you can keep the .v file unchanged.

 

Then re-run the simulation from command line. You can execute the commands in compile.sh, elaborate.sh and simulate.sh sequentially.

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Visitor joni_dambre
Visitor
331 Views
Registered: ‎10-29-2017

回复: Is VHDL supported for post-synth timing simulation in free HLS Web Pack? [Vivado 2018.3]

Hi,

I think this thread relates to problems we've been having for a while. I use Vivado (WebPack edition) in class for teaching VHDL-based digital design (beginner's class). However, ever since we migrated to Vivado, we've been having problems with timing simulation that are hard to reproduce. Some students get the warning mentioned in this thread, some don't. For some groups, timing simulations give all-zero delays and for other groups (in exactly the same assignment) they work. It has even happened that groups start having proper timing simulations, until suddenly delays disappear and we never can get them back. Thus far, we have tried to analyse a number of student projects, but we have found nothing that systematically relates to this problem.

Could anybody help?

Kindly,

 

Joni Dambre

 

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Observer abet
Observer
308 Views
Registered: ‎09-03-2018

回复: Is VHDL supported for post-synth timing simulation in free HLS Web Pack? [Vivado 2018.3]

Indeed that's my prblem too.
I remeber my professor launching a timing on my machine and it worked.

I've never been able to reproduce the result and could not understand why.
In my case it really seems to relate to the sdf generation. Do you have simlar issue @joni_dambre ? If so, share your sdf or at least the problematic lines please.

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Observer abet
Observer
304 Views
Registered: ‎09-03-2018

回复: Is VHDL supported for post-synth timing simulation in free HLS Web Pack? [Vivado 2018.3]

I edited the question title. I think it's worth mentioning that I'm on ubuntu 18.04 LTS here.

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Observer abet
Observer
298 Views
Registered: ‎09-03-2018

回复: Is VHDL supported for post-synth timing simulation in free HLS Web Pack? [Vivado 2018.3]

hi @graces 
So i tried to do what you suggested and I'm a bit confused (probably due to my inexperience).

I copy-pasted the content of your sdf over my sdf, I overwrote it.
To start, I should go through compile.sh if I understood well.
Here's my compile.sh file:

ExecStep()
{
"$@"
RETVAL=$?
if [ $RETVAL -ne 0 ]
then
exit $RETVAL
fi
}
echo "xvlog --incr --relax -prj cfg_tb_cmplx_vec_param_vlog.prj"
ExecStep xvlog --incr --relax -prj cfg_tb_cmplx_vec_param_vlog.prj 2>&1 | tee compile.log

echo "xvhdl --incr --relax -prj cfg_tb_cmplx_vec_param_vhdl.prj"
ExecStep xvhdl --incr --relax -prj cfg_tb_cmplx_vec_param_vhdl.prj 2>&1 | tee -a compile.log

How should I input this in the TCL console?
if I prompt

ExecStep xvlog --incr --relax -prj cfg_tb_cmplx_vec_param_vlog.prj 2>&1 | tee compile.log

The answer is :

invalid command name "ExecStep"

Similarly, writing

ExecStep()
{
"$@"
RETVAL=$?
if [ $RETVAL -ne 0 ]
then
exit $RETVAL
fi
}

Gives:

invalid command name "ExecStep()"

How should I step trhough the scripts you mentioned in Vivado?

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Xilinx Employee
Xilinx Employee
281 Views
Registered: ‎07-16-2008

回复: Is VHDL supported for post-synth timing simulation in free HLS Web Pack? [Vivado 2018.3]

The compile.sh is not supposed to be executed in Tcl console. It's executed in command line outside Vivado.

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