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Registered: ‎01-25-2020

Is it normal for Vivado simulations to be inconsistent, or am I not reading this correctly?

I'm trying to build a 8- way 4- bit multiplexer that chooses one of the 8 4-bit inputs to be sent to the output. The results of the simulation don't add up in some places

One place is marked by the yellow line in the figure. The input was meant to choose register 3, who carries a value of 3. And when you look at the output waveform (the label is also 'output') on the yellow line, it says 7 and the individual signals also add up to 7. But the value given for the output on the left hand side is 3, the expected answer. And the individual values below that give the correct binary representation of 3 (0011).

You can see what looks like a clear mistake in waveform of output(2) at the time marked. The waveform says HIGH, while the number in the table on the left says LOW.

The same thing happened for registers 0 and 1 as well, as you can see in the screenshot. The correct answers were next to the labels, while the waveform showed something else.

And in some other locations, it was the reverse. The waveform showed the right answer, the numbers were wrong.

Is this a thing that happens in Vivado simulations? I've heard they can be glitchy sometimes.

It's not a question of whether my code is right or wrong, it's why is the simulation giving me two different answers in two different places? Should I be believing the number, or the waveform? Or is it enough to have at least one of them right?

Screenshot (2).png
4 Replies
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183 Views
Registered: ‎06-21-2017

Re: Is it normal for Vivado simulations to be inconsistent, or am I not reading this correctly?

Can you share your code and test bench?

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159 Views
Registered: ‎06-21-2017

Re: Is it normal for Vivado simulations to be inconsistent, or am I not reading this correctly?

I see what you are saying about the simulation.  I don't have an explanation for that.  I wonder why you would code a multiplexer with a bunch of tri-state buffers instead of a case statement.  There are no tri-state buffers inside off a modern FPGA.  Tri-state buffers are only present on the IO pins.  It is true that most synthesis tools will infer a multiplexer from this code. I know that both ISE and Synplicity will.  I've never tried it with Vivado.

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Teacher
Teacher
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Registered: ‎07-09-2009

Re: Is it normal for Vivado simulations to be inconsistent, or am I not reading this correctly?

Yep , that output waveform is very wrong,

    is it at 3 or 7 ?  ,,  the code is very very confused,

 

I'd suggest this is a bug in simulator GUI .

 

Xilinx are going to ask , What version of what  tool are you using, on what OS ?

 

One thing, I have had similar, made a support case et all.

But it "corrected" when I zoomed in , and xilinx could not reporduce it.

 

As for you code, 

   a good start, me thinks you have a whay to go yet, 

we can critique if you want ?

 

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Registered: ‎01-25-2020

Re: Is it normal for Vivado simulations to be inconsistent, or am I not reading this correctly?

Aha, the tri-state buffers were part of a learning process. Is it possible that they could have been the reason for the strange simulation?
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