cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
330 Views
Registered: ‎02-18-2019

Issue while trying to simulate post-synthesis model

I try to simulate post-synthesis model in Vivado 2018.2. I use my testbench that I used when simulate behavourial model but can't to stimul signal. Below there's my waveform. Thanks in advance for your help.
Снимок1.PNG
0 Kudos
3 Replies
Highlighted
Moderator
Moderator
299 Views
Registered: ‎05-31-2017

Re: Issue while trying to simulate post-synthesis model

Hi @8150179miet ,

Can you please share the archived project to check this issue at our end ?

0 Kudos
Highlighted
Visitor
Visitor
285 Views
Registered: ‎02-18-2019

Re: Issue while trying to simulate post-synthesis model

Thank you for help. I found error myself. I tried to create netlist from my block design file. I replaced block design file with verilog file so it has worked.

0 Kudos
Highlighted
Moderator
Moderator
271 Views
Registered: ‎09-15-2016

Re: Issue while trying to simulate post-synthesis model

Hi @8150179miet ,

Glad to know that you were able to solve this issue. Can you please close this thread by marking your post with solution as accepted solution.

Thanks & Regards,
Sravanthi B
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
0 Kudos