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Contributor
Contributor
2,515 Views
Registered: ‎07-24-2009

Issue with assignment string parameter with escape characters to signal

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I checked issue with Vivado Simulator 2015.4 and 2016.4. Modelsim and Aldec do not have such problem.

 

Simple SV example:

 

parameter STR = "A\\nB";

wire [$size(STR)-1:0] str_i = STR;

 

Both STR and str_i have size 32. Hex representation of STR is 0x415c6e42 (4 symbols: A\nB). So, dual backslash is correctly translated to single in STR. But str_i is 0x00410a42. It seems that second translation of escape character (\n to 0x0a) was performed in the wire assignment. With the direct assignment str_i = "A\\nB" behavior is the same.

 

It works fine when wire is changed to logic (so, assignment is changed to initialization):

// Both STR and str_i are 0x415c6e42 

logic [$size(STR)-1:0] str_i = STR;

 

And finally working example

// STR, str_i and str_i2 are 0x415c6e42 

logic [$size(STR)-1:0] str_i = STR;
wire [$size(STR)-1:0] str_i2 = str_i;   // or logic

 

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Xilinx Employee
Xilinx Employee
4,647 Views
Registered: ‎08-10-2015

Re: Issue with assignment string parameter with escape characters to signal

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Hi @5506273,

 

This is bug in Vivado simulator, Issue(CR969375) reported to the factory.

 

 

Thanks,

Sunilkumar

View solution in original post

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Xilinx Employee
Xilinx Employee
4,648 Views
Registered: ‎08-10-2015

Re: Issue with assignment string parameter with escape characters to signal

Jump to solution

Hi @5506273,

 

This is bug in Vivado simulator, Issue(CR969375) reported to the factory.

 

 

Thanks,

Sunilkumar

View solution in original post

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