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Newbie idskot
Newbie
567 Views
Registered: ‎02-11-2018

Issue with clock timing in simulation using Vivado 2017.4

Hello, I'm currently taking an HDL class, and one of our assignments is to write a 16-bit register using Verilog. The issue I'm having is that even though I've used "always@(posedge clk)", operations are also occuring during some of the negative edges of the clock as well as the positive edges. (Attached is an image of the waveform)

 

If I change my clock such that the changing states of input/load values occur before/after the change in state of the clock, the register works properly.

 

Can anyone direct me in what I'm doing incorrectly?


My verilog code looks like this:

 

 

`timescale 1ns / 1ps

module Register( input [15:0] i,n input load, input clk, input [15:0] out ); reg [15:0] outVar; // Declare register to use in always statement always @(posedge clk) begin // When positive clock edge run: if (load == 0) begin // IFF load is high, assign output register = input register assign outVar = out; $display("outVar: %d", outVar); end else begin // Else IFF load is low, assign output = output (output[t+1] = output[t]) assign outVar = in; $display("outVar: %d, load = %d", outVar, load); end end assign out = outVar; // Assign final output as output registe endmodule

 

 


And my test bench is:

 

`timescale 1ns / 1ps

module Register_TestBench(

    );
    
    reg [15:0] in;              // 16-bit data input
    reg load, clk;              // load & clock Inputs
    wire [15:0] out;            // 16-bit data Output
    
    Register Register_0 (in, load, clk, out);
    
    // Test vectors
    
    initial begin
    in = 0;
    load = 0;
    clk = 0;
    #5;
    
    clk = ~clk;
    #5;
    

    in = 0;
    load = 1;
    clk = ~clk;
    #5;
    
    clk = ~clk;
    #5;
    
/*    in = 0;
    load = 0;
    clk = 0;
    #5;
    
    clk = ~clk;
    #5;    
  */  

    in = -32123;    
    load = 0;
    clk = ~clk;
    #5;
    
    clk = ~clk;
    #5;
    

    in = 11111;
    load = 0;
    clk = ~clk;
    #5;
    
    clk = ~clk;
    #5;
    

    in = -32123;
    load = 1;
    clk = ~clk;
    #5;
    
    clk = ~clk;
    #5;
    
                 
    in = -32123;
    load = 1;
    clk = ~clk;
    #5;
    
    clk = ~clk;
    #5;
    

    in = -32123;
    load = 0;
    clk = ~clk;
    #5;
    
    clk = ~clk;
    #5;  
    

    in = 12345;
    load = 1;
    clk = ~clk;
    #5;
    
    clk = ~clk;
    #5; 
    
   
    in = 0;
    load = 0;
    clk = ~clk;
    #5;
    
    clk = ~clk;
    #5;
    

    in = 0;
    load = 1;
    clk = ~clk;
    #5;
    
    clk = ~clk;
    #5;  

    in = 16'b0000000000000001;
    load = 0;
    clk = ~clk;
    #5;
    
    clk = ~clk;
    #5;
    
    load = 1;
    clk = ~clk;
    #5;
    
    clk = ~clk;
    #5;  
    

    in = 16'b0000000000000010;
    load = 0;
    clk = ~clk;
    #5;
    
    clk = ~clk;
    #5;
    
    load = 1;
    clk = ~clk;
    #5;
    
    clk = ~clk;
    #5;  
    

    in = 16'b0000000000000100;
    load = 0;
    clk = ~clk;
    #5;
    
    clk = ~clk;
    #5;
    
    load = 1;
    clk = ~clk;
    #5;
    
    clk = ~clk;
    #5;  
    

    in = 16'b0000000000001000;
    load = 0;
    clk = ~clk;
    #5;
    
    clk = ~clk;
    #5;
    
    load = 1;
    clk = ~clk;
    #5;
    
    clk = ~clk;
    #5;  
    
   
    in = 16'b0000000000010000;
    load = 0;
    clk = ~clk;
    #5;
   
    clk = ~clk;
    #5; 

   load = 1;
   clk = ~clk;
   #5;
   
   clk = ~clk;
   #5; 
   
   
   in = 16'b0000000000100000;
   load = 0;
   clk = ~clk;
   #5;
   
   clk = ~clk;
   #5; 
   
   load = 1;
   clk = ~clk;
   #5;
  
   clk = ~clk;
   #5; 
  
  
   in = 16'B0000000010000000;
   load = 0;
   clk = ~clk;
   #5;
   
   clk = ~clk;
   #5; 
   
   load = 1;
   clk = ~clk;
   #5;
  
   clk = ~clk;
   #5; 
  
  
   in = 16'b0000000100000000;
   load = 0;
   clk = ~clk;
   #5;
   
   clk = ~clk;
   #5; 
   
   load = 1;
   clk = ~clk;
   #5;
  
   clk = ~clk;
   #5; 
   
   in = 16'b0001000000000000;
   load = 0;
   clk = ~clk;
   #5;
   
   clk = ~clk;
   #5; 
   
   load = 1;
   clk = ~clk;
   #5;
  
   clk = ~clk;
   #5; 
   
   in = 16'B1111111111110111;
   load = 0;
   clk = ~clk;
   #5;
   
   clk = ~clk;
   #5; 
   
   load = 1;
   clk = ~clk;
   #5;
  
   clk = ~clk;
   #5;     
   

   in = 16'B1111111111011111;
   load = 0;
   clk = ~clk;
   #5;
   
   clk = ~clk;
   #5; 
   
   load = 1;
   clk = ~clk;
   #5;
  
   clk = ~clk;
   #5;         
   
   in = 16'B1011111111111111;
   load = 0;
   clk = ~clk;
   #5;
   
   clk = ~clk;
   #5; 
   
   load = 1;
   clk = ~clk;
   #5;
  
   clk = ~clk;
   #5;     
    end    
    
    end                                          
endmodule

 

 

Any help would be super appreciated! Thank you.

 

Capture.PNG
0 Kudos
1 Reply
Moderator
Moderator
553 Views
Registered: ‎03-16-2017

Re: Issue with clock timing in simulation using Vivado 2017.4

Hi @idskot

 

The issue here is you have used assign statement on reg outVar. Just change your source file as shown below and you will see that the out signal changes its states on posedge clock only. 

 

forum33.JPG

 

And the output will shown as below on posedge clock only. 

 

forumm.JPG

 

And make your out signal as output as it works as an output here.  output [15:0] out;

 

Regards,

hemangd

 

 

Regards,
hemangd

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