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Contributor
Contributor
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Registered: ‎02-25-2018

JTAG debug

Altera based design contained IP core "sld_virtual_jtag" for JTAG communication between FPGA soft core and system, same designe i want to  implement using xilinx FPGA board.

Is any IP core is available to replace sld_virtual_jtag IP core of altera to its equivalent IP core in xilinx.

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Xilinx Employee
Xilinx Employee
524 Views
Registered: ‎05-22-2018

Hi @khyam,

 

I am not sure whether it is going to work, but as the "sld_virtual_jtag" is a JTAG Interface you can check with the Xilinx JTAG interface(take reference from snapshot):

 

Capture_JTAG.JPG

 

Thanks,

Raj.

 

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