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Contributor
Contributor
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Registered: ‎06-25-2014

Keep multi-dimensional arrays from generate of multiple modules in netlist via 'write_verilog'

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I have a systemverilog module I wish to simulate post-synthesis and post-implementation with Vivado 2017.2 using the write_verilog tcl command.

The DUT top module is parameterised and this parameterisation generates 3 instantiations of another module. The outputs of which are arrays and so go into 2D multi-dimesional arrays ports on the top module.

Vivado appears to escape these multi-dimension arrays into separate ports. Hence ports in the RTL like..

   output logic [2:0] [31:0] m_axis_tdata,

..in the netlist become..

    output [31:0]\m_axis_tdata[2] ;
    output [31:0]\m_axis_tdata[1] ;
    output [31:0]\m_axis_tdata[0] ;

..I've found the following previous post but the answer is useless..

    https://forums.xilinx.com/t5/Synthesis/Keeping-port-name-same-after-synthesis/td-p/844752

....Steve

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Xilinx Employee
Xilinx Employee
153 Views
Registered: ‎07-16-2008

I'm afraid multi-dimensional array has to be expanded to vectors in synthesized netlist.

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Xilinx Employee
Xilinx Employee
154 Views
Registered: ‎07-16-2008

I'm afraid multi-dimensional array has to be expanded to vectors in synthesized netlist.

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post