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Registered: ‎09-28-2018

Kintex-7 KC705 External Input through XADC

Hello,

 

I am very new to FPGA's and was trying to connect external input through the XADC to Matlab/Simulink. I was going off an example from this link:

 

https://www.mathworks.com/help/supportpkg/xilinxfpgaboards/examples/read-temperature-sensor-data-from-xilinx-fpga-board-using-fpga-data-capture.html

 

I am using the Kintex-7 KC705 board not the ZedBoard or VC707 described. The data I obtain from the DataCaptureApp is the not the expected result and I believe it to be a problem with the I/O port designations. Matlab generates the VHDL files and the constraint file but the constraint file does not include the correct port locations. The bit width of the data going to the XADC is 12 and I am using the JTAG connection to Matlab. I am trying to use these ports:

 

set_property PACKAGE_PIN AB25 [get_ports XADC_GPIO_0]

set_property IOSTANDARD LVCMOS25 [get_ports XADC_GPIO_0]

set_property PACKAGE_PIN AA25 [get_ports XADC_GPIO_1]

set_property IOSTANDARD LVCMOS25 [get_ports XADC_GPIO_1]

set_property PACKAGE_PIN AB28 [get_ports XADC_GPIO_2]

set_property IOSTANDARD LVCMOS25 [get_ports XADC_GPIO_2]

set_property PACKAGE_PIN AA27 [get_ports XADC_GPIO_3]

set_property IOSTANDARD LVCMOS25 [get_ports XADC_GPIO_3]

set_property PACKAGE_PIN J24 [get_ports XADC_VAUX0N_R]

set_property IOSTANDARD LVCMOS25 [get_ports XADC_VAUX0N_R]

set_property PACKAGE_PIN J23 [get_ports XADC_VAUX0P_R]

set_property IOSTANDARD LVCMOS25 [get_ports XADC_VAUX0P_R]

set_property PACKAGE_PIN L23 [get_ports XADC_VAUX8N_R]

set_property IOSTANDARD LVCMOS25 [get_ports XADC_VAUX8N_R]

set_property PACKAGE_PIN L22 [get_ports XADC_VAUX8P_R]

set_property IOSTANDARD LVCMOS25 [get_ports XADC_VAUX8P_R]

 

The DataCaptureApp runs and the connection is fine but is always waiting for the trigger and will not record anything. Any help would be appreciated, thank you!

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