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Registered: ‎12-04-2018

Logic simulation of IP (PLL), error solution method

I would like  to perform logic simulation of IP (PLL). The simulator uses ModesSim batch mode.
However, when I run the simulation, an error occurs.
Please tell me how to solve this error.

I will attach the following.
  Error log (error.log)
  Test environment (
  Project file (
Best Regards,
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Registered: ‎09-15-2016

Hi @hwtodt ,

I see that you are using Vivado 2018.2 and in modelsim 2019.1 you came across the below error:

Error: (vsim-3033) Instantiation of 'clk_wiz_0_clk_wiz' failed. The design unit was not found.
# Time: 0 ns Iteration: 0 Instance: /top/clk_wiz_0 File: ./clk_wiz_0_2/clk_wiz_0.v Line: 78
# Searched libraries:
# D:/home/nishitomo/work/ip/sim/work

From the error message looks like the specified design unit could not be found for instantiation. 

Hence, in your project can you please try adding the top.v test bench file instantiating the IP and then export the simulation scripts using export_simulation command (file --> export --> export simulation) to run standalone simulation in modelsim. Then try comparing your scripts with the tool generated ones to check if there are any missing commands.

I have tried this at my end and with the attached scripts i was able to simulate the clocking wizard IP without any issues in modelsim.


Thanks & Regards,
Sravanthi B
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

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