07-12-2012 01:43 PM
Hey all, I have this bluespec code that incorporates a core generated by Xilinx. This core used by Xilinx uses a Xilinx primitive called "MMCM_ADV".
07-12-2012 06:02 PM
How did you "link Xilinx's verilog primitive path to Modelsim"? Did you run simulation in Modelsim standalone? What command did you use?
If you have pre-compiled Xilinx simulation libraries, please make sure "unisims_ver" library is referenced in vsim command.
07-12-2012 07:15 PM
By "link Xilinx's verilog primitive path to Modelsim", I mean that under the Xilinx folder, I found verilog files for some of the Xilinx primitives such as MMCM_ADV under the folders:
As such, I included the directories above as libraries to look into when I generated the modelsim binary executables.
However, it seems that when I try to look at those primitive verilog files, all those files contain are the inputs/outputs declarations but none of the actual logic.
07-16-2012 04:47 PM
You referred to the wrong directory. The MMCM_ADV primitive is located at $XILINX/verilog/src/unisims.