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zhangka12
Visitor
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Registered: ‎07-12-2012

MMCM_ADV

Hey all, I have this bluespec code that incorporates a core generated by Xilinx. This core used by Xilinx uses a Xilinx primitive called "MMCM_ADV".

When I simulate the code on ISIM, the design works perfectly.
However, when I try to then simulate it in model sim, it doesn't work. I've narrowed (at least) part of the problem down to this Xilinx primitive MMCM_ADV. It has 3 inputs (which I confirmed is being inputted correctly) and multiple outputs. I've noticed that the outputs from this modules are incorrect (Z or X) when simulated from modelsim but not in ISIM even though I've confirmed that in both cases, the inputs are all the same.
Additionally, I know that I linked Xilinx's verilog primitives path to modelsim such that modelsim knows where to search.
Also, I found that I have modelsim 6.4b, which is the minimum version needed according to XIlinx: http://www.xilinx.com/support/documentation/ip_documentation/mmcm_module.pdf
Anyone encountered a similar problem to this and knows how to solve it?
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graces
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Registered: ‎07-16-2008

How did you "link Xilinx's verilog primitive path to Modelsim"? Did you run simulation in Modelsim standalone? What command did you use?

 

If you have pre-compiled Xilinx simulation libraries, please make sure "unisims_ver" library is referenced in vsim command.

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zhangka12
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Registered: ‎07-12-2012

By "link Xilinx's verilog primitive path to Modelsim", I mean that under the Xilinx folder, I found verilog files for some of the Xilinx primitives such as MMCM_ADV under the folders:

 

verilog/xeclib/unisims

and 

verilog/src/unimacro

 

As such, I included the directories above as libraries to look into when I generated the modelsim binary executables.

 

However, it seems that when I try to look at those primitive verilog files, all those files contain are the inputs/outputs declarations but none of the actual logic.

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graces
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Registered: ‎07-16-2008

You referred to the wrong directory. The MMCM_ADV primitive is located at $XILINX/verilog/src/unisims.

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Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs.
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