Measuring energy consumption using Vivado Report Power?

[laundy]

Hello everyone,

I'm using Vivado 2019.2. My goal is to measure/calculate the energy consumption of my Verilog HDL code. As I was not able to find a proper feature in Vivado for achieving this directly, I implemented my design, did a post-implementation functional simulation to create a SAIF file and used this for the Report Power functionality (including a clock constraint at 100 MHz). This produces a total power with a high confidence but (if I understand it correctly) total power equals the maximum power that is required by the design. As a result, as this value could be only valid for, lets say, one clock cycle, it is not a representative "average" that I can use for calculating the energy taking the number of clock posedges into account (J = W * s).

In addition, it looks like the Report Power report does not provide another power value like average or at a specific time during the simulation.

Is there something I've overlooked? Could anybody of you give me a hint what I need to do to achieve a more or less reliable energy measurement?

Furthermore, I'm wondering how the delay for my clock register in my testbench influences the Report Power analysis. Does a delay of #5 in combination with a 100 MHz clock mean that one clock cycle lasts 10ns or 50ns?

reg clk;
always #5 clk <= ~clk;

Thanks in advance!

Regards,

Johannes

[calibra · Accepted solution]

For a SAIF simulation the reported power is the average over the simulation time.

To be accurate you must simulate a large number of clock cycles which is of course very slow.

But the most difficult factor for getting an accurate power estimation is that the design activity needs to be realistic. It should represent the typical or worst case scenario for data coming into the simulated block.

[laundy]

Thank you very much for the fast reply!

Do you know about a source that shows that this is actually the case? I was studying UG997 and UG907 intensively but wasn't able to find this information.

As I'm implementing well-defined algorithms were the inventors provide test vectors, my testbench is exactly describing this behavior. So I hope that the design activity is reflecting this case properly.

Do you have any idea about the delay thing?

[calibra]

"Do you have any idea about the delay thing?"

Sorry but I don't understand.

[laundy]

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@laundy wrote:

Furthermore, I'm wondering how the delay for my clock register in my testbench influences the Report Power analysis. Does a delay of #5 in combination with a 100 MHz clock mean that one clock cycle lasts 10ns or 50ns?

reg clk;
always #5 clk <= ~clk;

---

I'm referring to my second question that is about how a delay in the testbench for the clock register influences the overall clock cycles. In other words: Does a delay of #5 for each toggle of the clock register means that my design is actually running five times slower than with a delay of #1 or is this ignored by the simulation engine and Report Power?

[calibra]

Of course the Report Power take into account the clock frequency.

More precisely, SAIF file contains for each net the toggles per second.

Roughly speaking the power is proportional to the clock frequency plus the static power which is usually small.