cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Observer
Observer
8,926 Views
Registered: ‎09-13-2015

Memory Declaration and instantiation

Jump to solution

In my high level design I instantiated memory which would take a contantenate signal from two counters, but I'm getting all sort of errors such as the following:

 

I've also attached my high level vhd file wich comprises the component declaration and instantiation.

 

ERROR:HDLCompiler:69 - "/../clock.vhd" Line 85: <wea> is not declared.
ERROR:HDLCompiler:69 - "./../clock.vhd" Line 86: <addra> is not declared.
ERROR:HDLCompiler:69 - "../clock.vhd" Line 87: <addrb> is not declared.
ERROR:HDLCompiler:69 - "/../clock.vhd" Line 88: <dina> is not declared.
ERROR:HDLCompiler:69 - "/../clock.vhd" Line 89: <doutb> is not declared.
ERROR:HDLCompiler:192 - "/../clock.vhd" Line 89: Actual of formal out port doutb cannot be an expression
ERROR:HDLCompiler:854 - "/../clock.vhd" Line 28: Unit <structural> ignored due to previous errors.

 

 

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Moderator
Moderator
16,985 Views
Registered: ‎07-01-2015

Re: Memory Declaration and instantiation

Jump to solution

Hi @serge1973,

 

Try with the following code.

You have not declared wea,addra,addrb,dina,doutb in top module.

 

So during port map tool is throwing these errors.

Added the following lines to top module

signal wea : STD_LOGIC_VECTOR(0 DOWNTO 0);
signal dina : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal addra : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal addrb : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal doutb : STD_LOGIC_VECTOR(15 DOWNTO 0);

Please try with the attached .vhd and let us know the outcomes.

 

Thanks,
Arpan

Thanks,
Arpan
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

View solution in original post

0 Kudos
13 Replies
Highlighted
Moderator
Moderator
8,917 Views
Registered: ‎07-01-2015

Re: Memory Declaration and instantiation

Jump to solution

Hi @serge1973,

 

Which version of tool and the target device you are using?

 

Thanks,
Arpan

Thanks,
Arpan
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
8,915 Views
Registered: ‎05-20-2015

Re: Memory Declaration and instantiation

Jump to solution

Hi @serge1973,

 

 

You need to declare those as signals in your design with the width equivalent to what it is port-mapped to because they are not connected to any top-level ports.

Use the attached file.

 

Thanks,
Rajesh

0 Kudos
Highlighted
Observer
Observer
8,908 Views
Registered: ‎09-13-2015

Re: Memory Declaration and instantiation

Jump to solution

Hi @arpansur,

 

ISE 14.5 and I will be targetting Basys 2 board.

Thanks!

0 Kudos
Highlighted
Observer
Observer
8,904 Views
Registered: ‎09-13-2015

Re: Memory Declaration and instantiation

Jump to solution

Hi @rajeshtu,

I don't quite follow your response. I generated the block memory using the core generator within ISE14.5 tools which created some folder and vhd file. And like counters I thought I would do the same for the memory block by declaring its components and then instantiate them.

0 Kudos
Highlighted
Moderator
Moderator
16,986 Views
Registered: ‎07-01-2015

Re: Memory Declaration and instantiation

Jump to solution

Hi @serge1973,

 

Try with the following code.

You have not declared wea,addra,addrb,dina,doutb in top module.

 

So during port map tool is throwing these errors.

Added the following lines to top module

signal wea : STD_LOGIC_VECTOR(0 DOWNTO 0);
signal dina : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal addra : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal addrb : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal doutb : STD_LOGIC_VECTOR(15 DOWNTO 0);

Please try with the attached .vhd and let us know the outcomes.

 

Thanks,
Arpan

Thanks,
Arpan
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

View solution in original post

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
8,899 Views
Registered: ‎05-20-2015

Re: Memory Declaration and instantiation

Jump to solution

Hi @serge1973,
You have missed out the signal declarations in the code.
Please use the file attached above.

(When you instantiate a particular component in a design, then its ports must have either some connection to the top level (ports or signals) or it can be tied to any static value)


Thanks,
Rajesh

0 Kudos
Highlighted
Observer
Observer
8,879 Views
Registered: ‎09-13-2015

Re: Memory Declaration and instantiation

Jump to solution

All errors are gone. Thanks!

Do you think this part of the code is accurate? I've commmented out because I was also getting an error.

signal memory_address : std_logic_vector(15 downto 0);

memory_address <= address_h & address_v;

0 Kudos
Highlighted
Observer
Observer
8,878 Views
Registered: ‎09-13-2015

Re: Memory Declaration and instantiation

Jump to solution

Thanks! It's working now.

0 Kudos
Highlighted
Observer
Observer
8,874 Views
Registered: ‎09-13-2015

Re: Memory Declaration and instantiation

Jump to solution

I'm getting the following error I run the simuation

ERROR:HDLCompiler:288 - "./../clock.vhd" Line 96: Cannot read from 'out' object address_h ; use 'buffer' or 'inout'
ERROR:HDLCompiler:854 - "./../clock.vhd" Line 28: Unit <structural> ignored due to previous errors.

0 Kudos
Highlighted
Moderator
Moderator
7,425 Views
Registered: ‎07-01-2015

Re: Memory Declaration and instantiation

Jump to solution

Hi @serge1973,

 

You declared address_v and address_h as output but you are using it is as input in the following line

memory_address <= address_h & address_v;

 

That's the reason tool is throwing error.

So please change the declarations from out to inout and let us kow.

 

address_h : inout std_logic_vector(7 downto 0);
address_v : inout std_logic_vector(7 downto 0);

 

Please try with attached .vhd and verify if you are getting the same error or not.

 

Thanks,
Arpan

Thanks,
Arpan
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
0 Kudos
Highlighted
Observer
Observer
7,417 Views
Registered: ‎09-13-2015

Re: Memory Declaration and instantiation

Jump to solution

You're correct. Thanks a bunch!

0 Kudos
Highlighted
Moderator
Moderator
7,413 Views
Registered: ‎07-01-2015

Re: Memory Declaration and instantiation

Jump to solution

Hi @serge1973,

 

Glad to know your issue is resolved.

 

Just a suggestion:

It's good forum practice to create a new thread for different error message with subject as exact error message. It will be helpful for others having similar issue.

 

Thanks,
Arpan

Thanks,
Arpan
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
0 Kudos
Highlighted
Observer
Observer
7,403 Views
Registered: ‎09-13-2015

Re: Memory Declaration and instantiation

Jump to solution

Understood.

Thanks!

0 Kudos