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hisleo
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Registered: ‎09-02-2017

Mig 7 Series example simulation fail

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Hi,

 

I generate IP MIG (V7) for my design(2014 / 2016/2017, 3 versions of vivado tried).

For the example design, if I simulate by vivado itself, it is pass;  but if I simulate by VCS or IRUN, it failed on pi_phaselock_err.  

I could not find out the reason. Can anybody meet this problem?

3Q

 

 

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hisleo
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Registered: ‎09-02-2017

Finally, the problem was resolved. The reason is cause by my makefile, VE add incorrect option "+delay_mode_zero" whcich cause the error

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thakurr
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Registered: ‎09-15-2016

Hi @hisleo

 

What exactly the error you get while simulating in VCS or IRUN?

 

Regards

Rohit

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Regards
Rohit
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hisleo
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Registered: ‎09-02-2017

init_calibrate fail. I did basic waveform debug, find timeout when calibration fsm_state is 0x26.  Right FSM jump condition should  phaselock is high, but need appear.  

And when calibration start, most signal for ddr interface is still x state.  And from the waveform, I can watched that the input signals for phy_top is same for VCS and xsim simulation.

 

I would past waveform and log next monday

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vemulad
Xilinx Employee
Xilinx Employee
1,876 Views
Registered: ‎09-20-2012

Hi @hisleo

 

Try running the scripts ies_run.sh/vcs_run.sh located in project_1/mig_7series_0_example/mig_7series_0_example.srcs/sim_1/im
ports/sim folder.

 

Ensure that the version of VCS/IES used is supported with Vivado. Refer to vivado install and release notes for details.

Thanks,
Deepika.
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hisleo
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2,787 Views
Registered: ‎09-02-2017

Finally, the problem was resolved. The reason is cause by my makefile, VE add incorrect option "+delay_mode_zero" whcich cause the error

View solution in original post

0 Kudos