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jlevieux
Adventurer
Adventurer
445 Views
Registered: ‎09-12-2007

Missing Verilog Declaration For Zynq VIP Only During Post-Synthesis Simulation

I am getting error messages when I run a post-synthesis simulation that I do not get when I run a behavior simulation of the exact same test bench.

The messages are missing declarations for several terms used in the Zynq Verification IP.

ERROR: [VRFC 10-2991] 'fpga_soft_reset' is not declared under prefix 'inst'
ERROR: [VRFC 10-2991] 'pre_load_mem_from_file' is not declared under prefix 'inst'
ERROR: [VRFC 10-2991] 'read_data' is not declared under prefix 'inst'

I set the language to Verilog and the test bench file type to SystemVerilog, but I still get these errors.

Is it not possible to run the Zynq VIP as a post-synthesis simulation?

Thanks for your support!
John

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4 Replies
jlevieux
Adventurer
Adventurer
365 Views
Registered: ‎09-12-2007

Hi @hpbhat,

I had read those posts (and many others) prior to writing my post and unfortunately none of the fixes in those posts resolved the simulation errors I am getting with the Zynq VIP terms not being declared.

My behavioral simulation works fine, I just get a flood of FIFO collision warnings. On the other hand the post-synthesis simulation will not work at all and I get the fatal errors due to lack of declaration for the Zynq VIP terms. Perhaps it is not possible to post-synthesis simulate Zynq VIP?

Thanks for your support!
John

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jlevieux
Adventurer
Adventurer
279 Views
Registered: ‎09-12-2007

Hi @hpbhat,

I get the exact same declaration error messages when (a) I run the post-synthesis simulation of the unmodified example design of the Zynq VIP and (b) when I run my test bench containing Zynq VIP. So I conclude that post-synthesis simulation of Zynq VIP is not supported in Vivado. Please let me know if this is actually not the case.

If it is truly unsupported, can you please forward a request to Xilinx to consider adding the support in a future Vivado version?

Thanks for your support!
John

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markgraf
Adventurer
Adventurer
140 Views
Registered: ‎04-04-2018

Put me down as requesting some type of post synthesis/post implementations support. I know there concerns with the other peripherals, but seems they could be dummied out some way.

Also, I wonder if there will be similar limitations with Versal and other future devices.

Steve Markgraf - Distinguished FPGA Design & Support Engineer E5-E
www.designlinxhs.com
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