05-22-2019 09:53 AM
I'm trying to simulate the example PCIe DMA Subsystem (4.1) project, with modelsim, from within vivado.
When modelsim starts though, and things are loaded, there is eventually an error:
# ** Error: (vsim-3033) C:/Xilinx/Vivado/2018.3/data/verilog/src/unisims/PCIE_3_1.v(8089): Instantiation of 'SIP_PCIE_3_1' failed. The design unit was not found.
# Time: 0 fs Iteration: 0 Instance: /board/RP/pcie3_uscale_rp_top_i/pcie3_uscale_core_top_inst/genblk2/pcie3_uscale_top_inst/pcie3_uscale_wrapper_inst/PCIE_3_1_inst File: C:/Xilinx/Vivado/2018.3/data/verilog/src/unisims/PCIE_3_1.v
# Searched libraries:
# Error loading design
Line 8089 is instantiating something called SIP_PCIE_3_1
When the 'Compile Simulation Libraries' was carried out, there WAS one failure, for the ldpc_v2_0 library, but I don't need anything from that - I think!
The modelsim distributors can't really help as there is no trace of anything called SIP_PCIE_3_1 in the expected directories.
Can someone at Xilinx give us some insight please?
The project simulates fine with vivado's own simulator, but it is as if something is missing when compiling the libraries for modelsim.
Windows 10 Pro, x64
Modelsim DE 10.6c. (Tried both 32 and 64-bit).
05-24-2019 11:45 AM
Hi @mark_sa ,
Can you please share the compile_simlib.log file to check. can you please try using the file --> export --> export_simulaiton command to export the simulation scripts for your design with -lib_map_path option pointing to the compiled libraries and check if you are still facing the issue.
05-28-2019 03:44 AM
05-28-2019 06:02 AM
Hi again bandi.
Ah, there IS something called SIP_PCIE_3_1. In C:\Xilinx\Vivado\2018.3\data\secureip\pcie_3_1 is a file called pcie_3_1_001.vp. Has this not been compiled by 'compile_simlib' or something?
05-28-2019 06:48 PM
It should be compiled to 'secureip' library, which I see within the searched libraries from the transcript.
Do you see 'SIP_PCIE_3_1' if you expand 'secureip' library in the Library window in Modelsim?
05-29-2019 03:53 AM
Thanks for helping!
No, I don't see it in there. In fact, only 5 modules called SIP_anything. (See attached). Most modules just have a 7 hex digit name, and no path.
cheers for now,
05-29-2019 07:18 AM
.....I should add, its an artix7 project. Naturally, I had that family selected when I ran 'Compile Simulation Library' tool. The SIP_PCIE3_3_1 does not get compiled when the artix7 family is selected. .... or Kintex7, Virtex7, Spartan7 or Zync-7000. But it DOES if Kintex-Ultrascale is selected!
But now there are errors for B_GTPE2_CHANNEL, B_GTPE2_COMMON and B_PCIE_2_1.
Maybe these modules will get compiled in correctly if I select an FPGA family that I haven't tried yet.
Its looking like I will have to compile for ALL the families, even though I should only need to select the Artix7....
And its a slow process.... I'll let you know.
06-04-2019 03:18 AM
I've just installed Vivado 2019.1 in the thin hope that the problem goes away.... but it doesn't. The secure_ip library has very similar contents to my other post, nothing like yours that has loads of modules beginning with SIP.
There are also 2 libraries that fail to compile with 'compile_simlib, namely 'ldpc_v2_0_3' and 'qdma_v3_0_1'.
This a fresh installation today, straight out of the box.
What have we done wrong, or missed out?
08-08-2019 06:53 PM
@mark_sa Sorry just saw the update.
For 2019.1, the compatible Modelsim version is 10.7c.
Can you share the new compile_simlib.log for a look? And what is the exact error message with the newly compiled libraries?
08-09-2019 02:51 PM
Thank you for interest. I just resolved this issue by setting the options in the "compile simulation libraries" as below -
08-11-2019 08:14 PM
You mean using Questasim version 2019.3 resolves the issue?
Please mark the solution if the issue is clear now.
08-12-2019 11:23 AM
What worked for me was to select Family = "All"
Don't know if Questa Sim makes a difference. That is what I use haven't tried this for other simulators.