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Scholar
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Registered: ‎04-04-2014

Mixed vs VHDL Simulation Issues (generally and specifically for Aurora)

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Hi,

 

The is to report a problem and ask a question at the same time. We are using 2017.2 on Windows 10.

 

Myself and a colleague were running test benches no the same IP core and configuration but only one of us saw it working as expected. The core was an Aurora 64B/66B and one of us wasn't seeing channel/link up.

 

After an entire day chasing the problem (through opening our respective projects on each others PCs, generating example projects etc..) we worked out the problem. One of us was running a mixed sim language and one VHDL sim language. Both of us use VHDL as our main language in our projects.

 

So, it turns out the core would only work if using mixed language. This ensured the IP netlist and all generated files for the IP were verilog, whereas the other made the netlist VHDL and the rest verilog. This didn't work.

 

Obviously both should work, is this a bug? Should I now always make sure to used mixed language for these situations? 

 

Thanks

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Registered: ‎11-09-2015

Hi @mistercoffee,

 

I agree, but I have asked for an error (maybe with a way to disable this error). This way the user is directly aware of this (does not need to go through all the log).

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

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Registered: ‎11-09-2015

Hi @mistercoffee,

 

This is not a bug. The PG074 mentions that the Aurora IP sources are in verilog:

aurora.PNG

So it is expected that the simulation in VHDL only is not working.

 

However, this is not fully clear as the table for the IP says that the designs files are in RTL (which would mean Verilog + VHDL).

aurora2.PNG

I have asked to change this in the next version of the documentation

 

But yes, you should always use mixed language for simulation as some IPs are only available in VHDL and some others only in Verilog (in most cases there are at least in verilog but there is some exceptions)

 

Best Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Registered: ‎04-04-2014

@florentw wrote:

 


So it is expected that the simulation in VHDL only is not working.

 


Ok, I agree it is not a bug and I get the idea but I'm not sure I would agree with this statement here. The problem is that the example code and the IP netlist are in different languages. Both of these are created by the tool in a language determined by the project setting and setting the project to sim language VHDL is a valid setting that gives no warnings or errors.

 

I think expecting the user to know that this combination would not result in a working simulation is expecting too much. I clicked on the Aurora IP in my project and asked to "Open Example Design". What I would expect to follow is a working example.

 

Of all the pretty unnecessary (and sometimes false) warnings I would think a warning here would be more than warranted giving the likely implications don't you think? By all means put something in the documentation for the core but a tool warning would be a good idea too.

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Registered: ‎08-01-2012
What it needs, is if the user generates the Aurora in VHDL, the simulation VHDL should have an assert like:

assert (false) report "Aurora core simulation is not supported in VHDL" severity failure;
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Registered: ‎11-09-2015

Hi @mistercoffee,

 

The warning or error is actually a good idea. I have suggested this to development (simulator gives an error if the target langage is verilog while the target language is VHDL (and same reciprocally)).

 

@richardhead, it looks like a good idea but this would need having a check on every IP. The logistic is more complex to be sure it is correctly implemented on each IP.

 

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Registered: ‎04-04-2014

I think a warning is a good idea because even if the user is aware of the compatibility issue the setting could be made in error. It then takes quite a lot to work out what was wrong. It really wasn't obvious to me that the netlist was in VHDL until I went down the example hierarchy about 6 levels.

 

 

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Registered: ‎11-09-2015

Hi @mistercoffee,

 

I agree, but I have asked for an error (maybe with a way to disable this error). This way the user is directly aware of this (does not need to go through all the log).

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

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