03-06-2010 11:14 AM
Hi, I have a problem with reading file which looks like this:
and here's vhdl code:
entity data_gen is
fpga_clk : in std_logic;
data_out : out std_logic_vector(9 downto 0)
architecture gen of data_gen is
function to_std_logic(c: character) return std_logic is
variable sl: std_logic;
case c is
when 'U' =>
sl := 'U';
when 'X' =>
sl := 'X';
when '0' =>
sl := '0';
when '1' =>
sl := '1';
when 'Z' =>
sl := 'Z';
when 'W' =>
sl := 'W';
when 'L' =>
sl := 'L';
when 'H' =>
sl := 'H';
when '-' =>
sl := '-';
when others =>
sl := 'X';
function to_std_logic_vector(s: string) return std_logic_vector is
variable slv: std_logic_vector(s'high-s'low downto 0);
variable k: integer;
k := s'high-s'low;
for i in s'range loop
slv(k) := to_std_logic(s(i));
k := k - 1;
file IN_FILE : text open read_mode is "video_stream_very_short.txt";
variable DATA_LINE : line;
variable DATA_STRING : string(1 to 10);
variable TEMP : std_logic_vector(9 downto 0);
exit when endfile(IN_FILE);
TEMP := to_std_logic_vector(DATA_STRING);
wait until rising_edge(FPGA_CLK);
DATA_OUT <= TEMP;
ModelSim SE compiles this file without any errors or warnings but when I try to run simulation this message pops out:
** Fatal: (SIGSEGV) Bad pointer access.
# Time: 0 ps Iteration: 0 Process: /pixel_buffer_tb/pal_decoder/line__86 File: data_gen.vhd
# Fatal error in Process line__86 at data_gen.vhd line 93
# Executing ONERROR command at macro ./sim_data_gen.do line 79
Line 93 is:
Any ideas what I'm doing wrong? I have read lots of examples describing how file reading should be done and according to them my code is just fine, but sim won't go. I'll be really greatful for any word of advice.
03-08-2010 02:02 AM
I can't say it for sure, but sometimes it's just a Carriage Return too much or missing.
So, check your data file at the end:
Are there empty lines?
Are there spaces after the data?
Is the last line a Data field without CR/NL?
Check your file, and try some variants.
Maybe it helps.
Have a nice simulation
03-08-2010 08:15 AM