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Visitor
Visitor
1,304 Views
Registered: ‎11-16-2018

ModelSim can't simulate clock buffers (IBUF/BUFG)

The code I'm working on uses a couple of clock buffers and a mux to clock the transmit and receive controllers/RAMs for an UDP core (not my code)

  U1:  ibuf port map
      ( i => rx_clk,
        o => rx_clk_ibuf);

  U2: bufg port map
      ( i => rx_clk_ibuf,
        o => rx_clk_int);

  U3: bufgmux port map    
      ( i0 => tx_clk,
        i1 => rx_clk_int ,
        S  => enable_1Gb ,
        O  => tx_clk_int);

This works fine on final hardware, but in ModelSim both rx_clk_int and tx_clk_int become "Undefined" in waveform. I tried initializing the signals with '0' at declaration, but then they just remain 0 through the whole simulation instead. If I directly connect them it works however.

rx_clk_int <= rx_clk;
tx_clk_int <= tx_clk;

How can I get those buffers to work in simulation?

Or should I try use pragmas to select between the different code snippets depending on if it's synthesis or simulation? (I only know of "synthesis translate_on/off" though, so I don't know how to make simulator skip code)

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7 Replies
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Moderator
Moderator
1,274 Views
Registered: ‎04-24-2013

Hi @sicksystem,

Have you created a clock on tx_clk and rx_clk in your testbench?
If you have initialised them to zero and have no clock then they will remain zero.

Best Regards
Aidan

 

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Highlighted
1,266 Views
Registered: ‎06-21-2017

Have you compiled the Xilinx simulation libraries for ModelSim?

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Visitor
Visitor
1,249 Views
Registered: ‎11-16-2018

Yes, the rx_clk and tx_clk work fine, which is why the second code snippet I wrote is working.

To clarify, If I write the second code snippet, everything in the simulation works as expected. All components in the whole system act as I want them to, sending and receiving UDP packets etc. but as soon as I use the clock buffers instead of that direct assignment, the clocks become undefined.

With some experimentation I've come up with the temporary solution of keeping both snippets in the code

  U1:  ibuf port map
      ( i => rx_clk,
        o => rx_clk_ibuf);

  U2: bufg port map
      ( i => rx_clk_ibuf,
        o => rx_clk_int);

  U3: bufgmux port map 
      ( i0 => tx_clk,
        i1 => rx_clk_int ,
        S  => enable_1Gb ,
        O  => tx_clk_int);

-- synthesis translate_off
  rx_clk_int <= rx_clk;
  tx_clk_int <= tx_clk;
-- synthesis translate_on

It seems that ModelSim lets the direct assigments override the buffers, but this way the synthesis will keep using them.

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Visitor
Visitor
1,248 Views
Registered: ‎11-16-2018


@bruce_karaffa wrote:

Have you compiled the Xilinx simulation libraries for ModelSim?


If you mean the XilinxCoreLib, then yes it is compiled.

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Xilinx Employee
Xilinx Employee
1,238 Views
Registered: ‎07-16-2008

Is it a behavioral simulation or timing simulation? What is the clock frequency?

How do the BUFG input signals look like in the waveform?

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Visitor
Visitor
1,228 Views
Registered: ‎11-16-2018


@graces wrote:

Is it a behavioral simulation or timing simulation? What is the clock frequency?

How do the BUFG input signals look like in the waveform?


It is a behavioral simulation

clockbufs.png

rx_clk and tx_clk are inputs to buffers. Technically I can't say if BUFG is failing or not since the signal is Undefined already after IBUF, so of course BUFG becomes Undefined as well.

Frequency 25 MHz

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Xilinx Employee
Xilinx Employee
1,202 Views
Registered: ‎07-16-2008

It's strange that the output of IBUF remain undefined. It should be just a pass through.

Can you post the test case for a look?

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