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Observer eskull@0
Observer
397 Views
Registered: ‎11-10-2018

Modelsim 10.6c fails to start from Vivado 2018.2 on Ubuntu

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Hello,

Get the following failure message when launching simulation from Vivado :

Vivado_TCL_Console-Failed.png

Modelsim never opens.

Screen capture of Bash display of env (note first and last line…):

Env.png

I had copied the modelsim.ini file generated from the Xilinx simulation library folder, into the folder from where the Vivado project .xpr file is located.

I came across a couple of discussions on Xilinx forum. One in particular:

Xilinx_Forum_Post.png

So the first part of the reply above, the creation of a symbolic link to the linuxpe folder to start vsim, etc, (the 32 bit executables).

 

However, my install only has the linuxpe folder. So when vsim is started directly in a Bash shell (from…/Modelsim_dlx/bin), that vsim command links to the corresponding executable in linuxpe, and Modelsim starts right up.

So the above sym-link creation I think is unnecessary.

The next 3 lines in the above post specify options to be set with ‘32’ value. I played around with this in the Vivado Settings – Simulation window but I didn’t have any success here either:

Vivado_Sim_Settings.png

After setting those, Modelsim didn’t start and the same TCL console messages appeared.

Any suggestions appreciated.

 

Thank you.

 

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Xilinx Employee
Xilinx Employee
323 Views
Registered: ‎07-16-2008

回复: Modelsim 10.6c fails to start from Vivado 2018.2 on Ubuntu

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The simulation is run in incremental mode. I can see quite a few design modules are skipped compilation.

Would you please try open Simulation Settings, go to Advanced tab, and uncheck "Enable Incremental compilation" option?

Then run simulation again and see if re-compilation from the scratch allows you to proceed.

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Xilinx Employee
Xilinx Employee
339 Views
Registered: ‎07-16-2008

回复: Modelsim 10.6c fails to start from Vivado 2018.2 on Ubuntu

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It looks you set MIT_VCO_MODE to 32, which specifies 32-bit toolset to use on the platform.

To run 32-bit simulator from Vivado, run the following Tcl command prior to launching simulation.

set_property 32bit 1 [current_fileset -simset]

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Observer eskull@0
Observer
326 Views
Registered: ‎11-10-2018

回复: Modelsim 10.6c fails to start from Vivado 2018.2 on Ubuntu

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HI Graces,

 

Thank you for the helpful reply. I entered the string as you posted and then re-ran the sim. The Fail message did not occur. 

However, the simulation still did not start.

The TCL Console showed the following when it errored:

Vivado_TCL_Console_Sim_Error.PNG

I've attached the compile.log file - it shows no errors what so ever, tho there are a lot of warnings...

Any idea what might be wrong? 

 

Thank you again. 

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Xilinx Employee
Xilinx Employee
324 Views
Registered: ‎07-16-2008

回复: Modelsim 10.6c fails to start from Vivado 2018.2 on Ubuntu

Jump to solution

The simulation is run in incremental mode. I can see quite a few design modules are skipped compilation.

Would you please try open Simulation Settings, go to Advanced tab, and uncheck "Enable Incremental compilation" option?

Then run simulation again and see if re-compilation from the scratch allows you to proceed.

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
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Observer eskull@0
Observer
316 Views
Registered: ‎11-10-2018

回复: Modelsim 10.6c fails to start from Vivado 2018.2 on Ubuntu

Jump to solution

HI Graces,

Thanks again for the reply.

That worked, Modelsim started up, launched the simulation. 

Thank you for the valuable help.

Best Regards.

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