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Newbie jparrish
Registered: ‎07-15-2010

Modelsim Timing Issue - Virtex-6 coregenned FIFO

I've been experiencing some issues transitioning from older Virtex-4 LogiCore fifos (generated in ISE 10) to newer Virtex-6 fifos (generated in ISE 12).


When I simulate one of the older fifos using Xilinx ISE 10 simulation libraries, my data_out line changes exactly one clock cycle after rd_en goes high (see screenshot).


When I simulate one of the newer fifos using Xilinx ISE 12 simulation libraries and with the same testbench (only difference is which core is instantiated), the data_out line changes one clock cycle + 100 ps after rd_en goes high (see screenshot).


This 100 ps delay seems to be caused by the "SYNC_PATH_DELAY" after statement in the .vhdl models.  However, I also can see that the Virtex-4 models include this "SYNC_PATH_DELAY" yet they don't exhibit the same simulation behavior.


Note that I have tested this with both behavioral and structural coregen fifos.  The results are identical.


Is this behavior intended?  Ideally, I would like my Virtex-6 simulation to function identically to the Virtex-4 simulation so I can verify my logic still works correctly.

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