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uglykidjoe
Newbie
Newbie
9,754 Views
Registered: ‎05-09-2009

Modelsim and testbench

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Hello.

 

 

I can't get Modelsim PE to work with this code:

 

 

 

it displays these errors:

 

 

# ** Error: testbench1.vhd(72): near "constant": syntax error
# ** Error: testbench1.vhd(79): (vcom-1136) Unknown identifier "clk_period".
# ** Error: testbench1.vhd(79): Type error resolving infix expression "/" as type std.standard.time.
# ** Error: testbench1.vhd(81): (vcom-1136) Unknown identifier "clk_period".
# ** Error: testbench1.vhd(81): Type error resolving infix expression "/" as type std.standard.time.
# ** Error: testbench1.vhd(93): (vcom-1136) Unknown identifier "clk_period".
# ** Error: testbench1.vhd(93): Type error resolving infix expression "*" as type std.standard.time.
# ** Warning: [2] testbench1.vhd(95): (vcom-1090) Possible infinite loop: Process contains no WAIT statement.
# ** Error: testbench1.vhd(97): VHDL Compiler exiting
# ** Error: C:/Modeltech_pe_edu_6.5/win32pe_edu/vcom failed.
# Error in macro ./testbench1.fdo line 8
# C:/Modeltech_pe_edu_6.5/win32pe_edu/vcom failed.
# while executing
# "vcom -explicit -93 "testbench1.vhd""
 

 

-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 15:16:54 05/09/2009 -- Design Name: -- Module Name: C:/xilinx/10.1/ISE/RS232_locen_tx_rx/rs232_locen_rx_tx/testbench1.vhd -- Project Name: rs232_locen_rx_tx -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: rs232 -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY testbench1 IS END testbench1; ARCHITECTURE behavior OF testbench1 IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT rs232 PORT( RXD : IN std_logic; CLK : IN std_logic; LEDS : OUT std_logic_vector(7 downto 0); RST : IN std_logic ); END COMPONENT; --Inputs signal RXD : std_logic := '0'; signal CLK : std_logic := '0'; signal RST : std_logic := '0'; --Outputs signal LEDS : std_logic_vector(7 downto 0):= "00000000"; BEGIN -- Instantiate the Unit Under Test (UUT) uut: rs232 PORT MAP ( RXD => RXD, CLK => CLK, LEDS => LEDS, RST => RST ); -- No clocks detected in port list. Replace <clock> below with -- appropriate port name --signal ENDSIM: boolean; constant clk_period: time := 20 ns; CLK_GEN: process begin --if ENDSIM = false then CLK <= '0'; wait for clk_period/2; --CLK_PERIOD CLK <= '1'; wait for clk_period/2; --else wait; --end if; end process; -- Stimulus process stim_proc: process begin RST <= '1', '0' after 5*clk_period; end process; END;

 

 

Any ideas?

 

 

 

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Accepted Solutions
chenhongyi123
Visitor
Visitor
11,511 Views
Registered: ‎01-05-2009

hi uglykidjoe,

line 72 " constant clk_period: time := 20 ns;  "  isn't in it's position

it is beteen

 ARCHITECTURE behavior OF testbench1 IS

...........

 constant clk_period: time := 20 ns; 

 ..........

BEGIN

 

 

 

 

View solution in original post

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2 Replies
chenhongyi123
Visitor
Visitor
11,512 Views
Registered: ‎01-05-2009

hi uglykidjoe,

line 72 " constant clk_period: time := 20 ns;  "  isn't in it's position

it is beteen

 ARCHITECTURE behavior OF testbench1 IS

...........

 constant clk_period: time := 20 ns; 

 ..........

BEGIN

 

 

 

 

View solution in original post

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uglykidjoe
Newbie
Newbie
9,726 Views
Registered: ‎05-09-2009
Oh. I didn't saw that... Works ok now, thanks.
Message Edited by uglykidjoe on 05-10-2009 01:08 AM
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