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Adventurer
Adventurer
11,433 Views
Registered: ‎04-15-2013

Modelsim not updating IP blocks in simulations

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Hey all,

 

I'm having a problem with modelsim that I've never encountered. simply put Modelsim is not updating my blocks of code when I try to simulate. At first I was getting an issue with the block not being fully bound in the design, so made sure the component declaration was correct and it worked. However parts of my design were not correct so I made some modifications to my HDL. Well, no matter what modifications I make none of them are reflected in the simulation, it always just looks like the old version is still in there. I have gotten a warning that an IP block has been modified after it's been compiled so I think that may be where the disconnect is but I can't figure out how to update the compilation for the Modelsim to use.

 

I am trying to run the testbench using the pregenerated user_logic module as the top-level, if that matters. This block is also acting a bit funny in that it won't let me "create HDL instantiation template" on it.

 

I've used Modelsim for quite a while and this problem has me stumped. There are many Kudo's to be had for some help to my situation :)

 

Any help is appreciated.

- K

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Adventurer
Adventurer
19,251 Views
Registered: ‎04-15-2013

Re: Modelsim not updating IP blocks in simulations

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I figured it out!

 

So the issue with using the generated user block IP in a design then simulating through Modelsim is that the user_logic IP is a remote source for the project if the project is generated by the typical custom IP creation tool of EDK (in retrospect I should have included that bit of information, but I figured it would have been understood). So by making the user_logic a local project file then synthesizing the project, creating an HDL instantion templatein ISE, and then ensuring the template description matches the one in the testbench for instanting the component. the problem was solved. This may be a bug or maybe just the designers didn't expect me to be simulating Xilinx IP as a top-level in TB... which seems strange to me.

 

Thanks to all who took the time to read and respond.

 

Have a good one,

- K 

View solution in original post

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7 Replies
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Xilinx Employee
Xilinx Employee
11,418 Views
Registered: ‎02-06-2013

Re: Modelsim not updating IP blocks in simulations

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Hi

 

 

What tools and versions are you using ISE/VIvado and is it standalone or integrated flow.

 

Are you able to see the changes in the file  you have done reflected in the Modelsim source files?

 

What is the exact error or issue you are facing when you are trying to modify the test bench file

Regards,

Satish

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Adventurer
Adventurer
11,403 Views
Registered: ‎04-15-2013

Re: Modelsim not updating IP blocks in simulations

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Version 14.7 on ISE, using the integrated flow from ISE to Modelsim SE 10.2.


Are you able to see the changes in the file  you have done reflected in the Modelsim source files?

 


- No

 


 

What is the exact error or issue you are facing when you are trying to modify the test bench file


# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.testbench(behavior)#1
# ** Warning: (vsim-3473) Component instance "DUT_UL : user_logic" is not bound.
# Time: 0 ps Iteration: 0 Instance: /testbench File: UL_tb.vhd

 

that was the first warning I was getting. then I corrected my component instantiation, and that's when the simulation wouldn't update. There is no warning or error from either modelsim or ISE, just incorrect output data.

 

For Example, I modified the IP removing certain signals from the design then resimulated the design the design, but the signals still appeared in modelsim. that's how I know something is definitively wrong.

 

- K

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Xilinx Employee
Xilinx Employee
11,394 Views
Registered: ‎07-16-2008

Re: Modelsim not updating IP blocks in simulations

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Can you post the DO script generated by ISE? What's the exact warning that "an IP block has been modified after it's been compiled"?

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Xilinx Employee
Xilinx Employee
11,389 Views
Registered: ‎02-06-2013

Re: Modelsim not updating IP blocks in simulations

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Hi

 

After making the changes are you running the simulation again or doing the simulation in already opened modelsim.

 

If you simulate the desing with ISE instead of Modelsim,are the changes updating and simulation is correct.

 

If you are changing the design files in ISE and then moving to already opened modelsim the tool will ask you to reload the changes in the files or to keep the original files.

 

Are you seeing this message.

 

Regards,

Satish

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Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

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--------------------------------------------------​-------------------------------------------
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Adventurer
Adventurer
11,379 Views
Registered: ‎04-15-2013

Re: Modelsim not updating IP blocks in simulations

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Which script the .fdo?

No, it specifies the user_logic block that I modified but I don't know how to update the compilation.
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Adventurer
Adventurer
11,379 Views
Registered: ‎04-15-2013

Re: Modelsim not updating IP blocks in simulations

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I'm using the integrated flow, none of those messages you are mentioning are coming up. Everytime I'm running modelsim I'm rerunning the entire simulation, not just restarting it.

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Adventurer
Adventurer
19,252 Views
Registered: ‎04-15-2013

Re: Modelsim not updating IP blocks in simulations

Jump to solution

I figured it out!

 

So the issue with using the generated user block IP in a design then simulating through Modelsim is that the user_logic IP is a remote source for the project if the project is generated by the typical custom IP creation tool of EDK (in retrospect I should have included that bit of information, but I figured it would have been understood). So by making the user_logic a local project file then synthesizing the project, creating an HDL instantion templatein ISE, and then ensuring the template description matches the one in the testbench for instanting the component. the problem was solved. This may be a bug or maybe just the designers didn't expect me to be simulating Xilinx IP as a top-level in TB... which seems strange to me.

 

Thanks to all who took the time to read and respond.

 

Have a good one,

- K 

View solution in original post

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