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ashutosh.soman
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Registered: ‎01-11-2014

Modelsim runs too slow

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Hi,

 

I am working on an image analysis application based on microblaze. I am trying to simulate my microblaze design with modelsim. Now, the problem is, it takes about 10 sec to load the image in the accelerator. And the simulation is terribly slow and if I run it for 10 sec then i think it will take weeks. Is there any way to quickly put the simulation at the state it will be after 10 sec? (or somehow jump to 10 sec) and then run the simulation for 10 ms? That means, I wish to run the simulation once the image is loaded on the microblaze. Though it works on the actual board, i need to simulate it to do the energy profiling of the system.

 

Thanks in advance!

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eilert
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Registered: ‎08-14-2007

Hi,

Ok, now your question is more specific.

The answer is: No, you can't peek into the future.

The reason is that a synchronous logic design can be seen as a FSM which is very much the same as a cellular automaton.

And the CA theory proves that there is no state prediction or looking ahead (except for trivial machines, e.g. trivial counters). 

 

About your system:

The CPU seems OK,

The RAM might be sufficient if properly used by the OS.

HDD speed means (true) transfer speed for writing away the simulation data. 

It does not primarily matter how fast the bits are spinning in circles. :-)

 

For simulation the file writing is one of the major bottlenecks that can be optimized and give a true improvement.

 

The next better thing could be HW-Cosim.

Again: The testbench setup and data exchange is crucial to the performance.

Also, this way you might not get the VCD-file for feeding the XPowerAnalyzer.

But therefore you can use a power meter and measure the power consumption of your board directly.

There are boards available that offer special measurement points for this purpose.

 

And as a side effect you have already proven that your design is synthesizable and works on silicon.

 

Have a nice simulation

  Eilert

 

 

 

 

 

 

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hj
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Registered: ‎06-05-2013
Hi,
Is it vivado or ISE?

Please try to use Xilinx simulator & let us know the results.

Thanks
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For more information please refer to configuration resources https://forums.xilinx.com/t5/FPGA-Configuration/Configuration-Resources/m-p/753763/highlight/true#M5891
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ashutosh.soman
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Registered: ‎01-11-2014

Hi,

 

Thank you for the reply. I am using ISE to generate the system and then simulating it using modelsim. I also tried to use Isim but it took me about 8 hours to simulate for 2.5ms. So, infact, if there's method to speedup the process in ISim, that would work too! I an ready to try both the simulators in parallel.

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ashutosh.soman
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Also, after simulating, I need to generate SAIF file for XPowerAnalysis. (As far as I know, there isn't any direct method to generate SAIF file in ISim, and vcd generated was huge - 15GB) I am also trying to find ways to generate SAIF file in Modelsim.

 

Thank you,

Ashutosh

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eilert
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Registered: ‎08-14-2007

Hi,

the Simulator probably is the last thing to blame.

 

Unfortunately you don't give enough informations about your simulation setup for a qualified analysis of the situation..

 

You are simulating some Microblaze design:

             So you have a number of big IP cores and maybe some external RAM models.

You mention that your design is for Image processing:

             This means a real lot of data to be handled.

 

With this alone you give any simulator a hard time.

Also, what about the computer you are using for simulation? CPUs? RAM? HDD (transfer speed not size)?

Such a simulation requires top performance hardware.

 

 

Then you mention some "Acellerator" . What does this mean?

Are you doing some kind of Hardware-Cosimulation?

If so, whith which kind of FPGA-Board and what kind of interface are you using?

While HW-Cosim reduces the computation load of the simulating host PC, a bad interface design can cause a huge communication overhead that reduces the simulation performance of the whole setup.

 

And yes, sometimes such simulations can take weeks.

We once had a similar situation and in our case it was the DDR-Ram model that consumed most of the computation power.

 

 

Have a nice simulation

  Eilert

 

 

 

 

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ashutosh.soman
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Registered: ‎01-11-2014

Hi,

 

Thanks eilert for your reply. I am no blaming the simulator, and probably modelsim will also take the same amount of time as ISim. I was just enquiring about is there any way to do it faster. Or if there is a way to directly jump to a time, say, at 10 sec and then take the value change dump for 10ms because running simulation for 10s simulation time is not a feasible and practical solution.

 

The machine used is an intel i7 CPU, 8 GB ram and 7200 rpm HDD so that would not be of a problem i think. I agree the design is big and complex and will need time to process.

 

I  am not doing hardware co-simulation, the accelerator is a custom IP core we have created and we wish to analyze its power using xpower analyzer. So, infact, we need the simulation to generate vcd file for XPowerAnalyzer. Could you suggest a way to speed up the simulation, or is it not possible to speed it up. Also, is there any other way to generate vcd/saif file other than simulation, so that it could be faster?

 

 

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eilert
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Registered: ‎08-14-2007

Hi,

Ok, now your question is more specific.

The answer is: No, you can't peek into the future.

The reason is that a synchronous logic design can be seen as a FSM which is very much the same as a cellular automaton.

And the CA theory proves that there is no state prediction or looking ahead (except for trivial machines, e.g. trivial counters). 

 

About your system:

The CPU seems OK,

The RAM might be sufficient if properly used by the OS.

HDD speed means (true) transfer speed for writing away the simulation data. 

It does not primarily matter how fast the bits are spinning in circles. :-)

 

For simulation the file writing is one of the major bottlenecks that can be optimized and give a true improvement.

 

The next better thing could be HW-Cosim.

Again: The testbench setup and data exchange is crucial to the performance.

Also, this way you might not get the VCD-file for feeding the XPowerAnalyzer.

But therefore you can use a power meter and measure the power consumption of your board directly.

There are boards available that offer special measurement points for this purpose.

 

And as a side effect you have already proven that your design is synthesizable and works on silicon.

 

Have a nice simulation

  Eilert

 

 

 

 

 

 

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ashutosh.soman
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Registered: ‎01-11-2014

Hi,

 

Thanks for the reply! So, the simulation will take time. I can not do co-simulation as the board is accessed through university server and does not support measurement of power. :( Is there any other way to get decently correct idea of power consumption? Using XPowerAnalyzer? Can saif file be generated faster or it also needs simulation to run?

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bassman59
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Registered: ‎02-25-2008

@ashutosh.soman wrote:

Hi,

 

Thank you for the reply. I am using ISE to generate the system and then simulating it using modelsim. I also tried to use Isim but it took me about 8 hours to simulate for 2.5ms. So, infact, if there's method to speedup the process in ISim, that would work too! I an ready to try both the simulators in parallel.


Which version of ModelSim? You may have to spring the large dollars for the SE version.

----------------------------Yes, I do this for a living.
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ashutosh.soman
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Registered: ‎01-11-2014

I need it for less than a month, so i am using a trial version. Version : 10.2c

 

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ashutosh.soman
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Registered: ‎01-11-2014

Hi,

 

I was trying to run modelsim PE from XPS but it gives errors. So i tried to run modelsim externally. Now i could add all the modules but I got an error like this for my BRAM.

 

Loading lmb_bram_elaborate_v1_00_a.lmb_bram_elaborate(structure)
# Loading unisim.ramb36e1(ramb36e1_v)
# Loading unisim.rb36_internal_vhdl(rb36_internal_vhdl_v)
# ** Fatal: (vsim-7) Failed to open VHDL file "lmb_bram_combined_0.mem" in rb mode.
#
# No such file or directory. (errno = ENOENT)
# Time: 0 ps Iteration: 0 Process: /system_tb/dut/lmb_bram/lmb_bram/ramb36e1_0/TDP/RAMB36E1_TDP_inst/prcs_clk File: C:/Xilinx/14.2/ISE_DS/ISE/vhdl/src/unisims/primitive/RAMB36E1.vhd
# FATAL ERROR while loading design

 

I have mem files generated for my BRAM from my simulation in ISim. How can I add these to the simulation?

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graces
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Registered: ‎07-16-2008

Make sure the .mem file is placed in the same directory as the BRAM file used for simulation.

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