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Visitor
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Registered: ‎03-04-2019

Module not found in post synthesis functional simulation

I've been trying to figure this out since 2 days, and have tried different things suggested in other posts but nothing seems to work, I'd be grateful if anyone can help me figure this out.

My behavioral simulation and synthesis run fine but for some reason I'm not able to run the post synthesis simulation due the following error. I'm using Vivado 2018.2.

ERROR: [VRFC 10-93] isram is not declared under prefix UUT [/home/pr1498/project_cnn_ddr3/project_cnn_ddr3.srcs/sources_1/new/sim_TPU_test.v:478]

I've tried with flatten heirarchy to none, as suggested in https://forums.xilinx.com/t5/Simulation-and-Verification/Simulation-error-VRFC-10-2063-Module-not-found-while-processing/td-p/472796

But this makes no difference.

The iSRAM instance is created in top.sv file like this  :                 
           genvar xx;
           generate
               for(xx=0; xx < depth; xx=xx+1) begin : isram
                   mDualPort_SRW_SRAM     #    (
                                           .pIODATA_WIDTH(bit_width),
                                           .pADDR_WIDTH(iSRAMadrwidth), 
                                           .pRAM_DEPTH(`batchsize) 
                                       ) iSRAM  (
                                                  .iClk0(clk),    
                                           .iAddr0(iSRAMWriteAddress[xx]),    
                                           .ioData0(iMemIn[xx]),   
                                           .iChipSel0(iSMemWrite[xx]), 
                                           .iWriteEn0(iSMemWrite[xx]),
                                           .iReadEn0(1'b0),  
                                           .iAddr1(iSRAMReadAddress[xx]),    
                                           .ioData1(iMemOut[xx]),   
                                           .iChipSel1(iSMemRead[xx]),
                                           .iWriteEn1(1'b0), 
                                           .iReadEn1(iSMemRead[xx])   
                                       );
               end
           endgenerate 

 

And is accessed in sim_TPU_test.v file like this :

initial begin


`ifdef TPUmem0
    $readmemb("isram0.mem", uut_tpu.UUT.isram[0].iSRAM.rMem);  
`endif
`ifdef TPUmem1
    $readmemb("isram1.mem", uut_tpu.UUT.isram[1].iSRAM.rMem); 
`endif

I've tried my code without the TPUmem macros, but I still get the same error. Can anyone tell me what's wrong with my code and what I could do to fix it ?

I've attached pictures of design hierarchy. 

Thanks a lot!

hierarchy1.png
hierarchy2.png
hierarchy3.PNG
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3 Replies
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Moderator
Moderator
523 Views
Registered: ‎09-15-2016

Hi @pr1498 ,

Can you please share the archived project or the test case to check this issue at our end.

Thanks & Regards,
Sravanthi B
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Visitor
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Registered: ‎03-04-2019

Hi Sravanthi,

I've attached some files, I couldn't upload all files as the size exceeded the maximum limit for this forum. I don't think you will be able to run the code with the files I've uploaded, but there was no other option avaialble.

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Moderator
Moderator
446 Views
Registered: ‎09-15-2016

Hi @pr1498 ,

I have shared an EZMove package with you. Can you please attach the complete archived project and send it back to me.

 

Thanks & Regards,
Sravanthi B
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