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320 Views
Registered: ‎07-30-2019

Monitoring of the intermediate Netlist signals of a Primitive

I need to simulate the design by injecting the Design(VHDL) Entity Inputs and along with the by forcing the
internal Net list.

Let say I have Intermediate D-FlipFlop, Which I need to simulate the actual design by injecting Entity Inputs and
along with by forcing the D-input of D-FlopFlop and Capture the D-FlipFlop Output Q at different Time Intervals.

Can You please provide the solution for the following problem
Since I have multiple D-FF in my desing and I can't visually see the Outputs of all the D-FF during my
simulation time.
If I have only one single D_FF, I can visually see the Outputs as per Inputs. If I have multiple D-FF,
Its very difficult to monitor all signals.
What is the best way to solve the above problem.

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14 Replies
Scholar dpaul24
Scholar
312 Views
Registered: ‎08-07-2014

Re: Monitoring of the intermediate Netlist signals of a Primitive

sriharikumar.goud@gmail.com,

I need to simulate the design by injecting the Design(VHDL) Entity Inputs and along with the by forcing the internal Net list.

I did not understand this, what you are trying to do.

Why do you want to monitor the flop o/p for a netlist? Why won't you monitor them at the RTL level in simulation?

Try out the VHDL2008 feature of using 'Hierarchical Names' if you are trying to monitor specific outputs deep inside your design hierarchy.

 

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Scholar drjohnsmith
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298 Views
Registered: ‎07-09-2009

Re: Monitoring of the intermediate Netlist signals of a Primitive

Whats your level of experiance ?

 

Its typical in FPGA designs , to simulate the design.

 

Vivado has built in simualtor for that , as does ISE. Which are you using ?

 

Simulatoin alows one to examin in the waveform monitor all the signals in your design,

    You apply stimulus from your test bench , and monitor in the simulation the results.

 

try this

https://www.youtube.com/watch?v=6CpSlv1se7U

 

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Uploaded by BYU Digital Lab on 2018-01-25.
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289 Views
Registered: ‎07-30-2019

Re: Monitoring of the intermediate Netlist signals of a Primitive

I can simulate the at RTL level, where as I need to test some portion of logic at Gate Level.

Since  I can't read those netlist at RTL level. 

I need to log the output of logic 1(as a file) and logic 2 primitives of FPGAs along with the actual Desing Inputs.

Thats what my application.

12.PNG

 

 

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Scholar drjohnsmith
Scholar
282 Views
Registered: ‎07-09-2009

Re: Monitoring of the intermediate Netlist signals of a Primitive

thats what simulation alows you to do ,

   look at every node in the design,  not just the top level pins,

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276 Views
Registered: ‎07-30-2019

Re: Monitoring of the intermediate Netlist signals of a Primitive

Is it possible to log the intermediate outputs in the form TCL script or any other scripts.
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Scholar dpaul24
Scholar
275 Views
Registered: ‎08-07-2014

Re: Monitoring of the intermediate Netlist signals of a Primitive

sriharikumar.goud@gmail.com,

Seems like you need what is called the Vivado FPGA Editor tool for ISE it should be the ISE editor.

See here- https://www.xilinx.com/support/answers/67548.html

I have never used it (neither do most people, netlist editing is rarely done), so can't comment any further.

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Scholar drjohnsmith
Scholar
272 Views
Registered: ‎07-09-2009

Re: Monitoring of the intermediate Netlist signals of a Primitive

the simulator saves the waveform file for you of all th esignals your monitoring , which can be post processed by yourslef.

do you have the simulator working looking at all the nodes ?

   cna yo upost a screen shot

 

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251 Views
Registered: ‎07-30-2019

Re: Monitoring of the intermediate Netlist signals of a Primitive

gate1.PNG

 

 

In the above screen, when y_err is high, I need to capture the logs in different timing based on the different inputs given from A, B, C. Since these ports are not accessble to outside world, I can access only through the TCl commands if possible. is it possible to log the outputs y_err through the script.

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Adventurer
Adventurer
238 Views
Registered: ‎01-27-2008

Re: Monitoring of the intermediate Netlist signals of a Primitive

Hi sriharikumar.goud@gmail.com,

I haven't done this through TCL, and don't believe you can. However, as @drjohnsmith and @dpaul24  point out, you can do this through your testbench.

Perhaps a concrete example will help.

What I do is write a separate testbench file that has a few processes. You can directly instantiate this module in your testbench to keep the system manageable, neatly designed.

I use three processes in this file:

1. inital process to open the file for writing

initial begin
// tmp, reslo_file, suff are strings that create a full path name
fh_res_lo = $fopen({tmp, reslo_file, suff}, "wb"); $display("opening file for writing: %s", {tmp, reslo_file, suff});
end // initial begin

2. always process to write data, at any node in the model, to the file and use $time to capture the timing of said signals.

   always@(posedge clk) begin
      if (signal_proc_top_tb.uut.resolved_lo_data.ena) begin
	 $fwrite(fh_res_lo, "[%10t] %01X %05X %05X\n", $time,
		 signal_proc_top_tb.uut.resolved_lo_data.chan, 
		 signal_proc_top_tb.uut.resolved_lo_data.data[1],
		 signal_proc_top_tb.uut.resolved_lo_data.data[0]);

	 $fflush(fh_res_lo);
      end
end // always

3. initial process that waits for the testbench to stop running, then closes files.

 

You can scale this to capture whatever you need to file. Works like a charm.

Have fun,

Jerry

Scholar drjohnsmith
Scholar
230 Views
Registered: ‎07-09-2009

Re: Monitoring of the intermediate Netlist signals of a Primitive

Might be me, but you can show all the signals in the waveform window, not just the top one, just select the lower level module ,

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Adventurer
Adventurer
218 Views
Registered: ‎01-27-2008

Re: Monitoring of the intermediate Netlist signals of a Primitive

Good point!
Xilinx Employee
Xilinx Employee
199 Views
Registered: ‎07-16-2008

Re: Monitoring of the intermediate Netlist signals of a Primitive


@drjohnsmith  已写:

Might be me, but you can show all the signals in the waveform window, not just the top one, just select the lower level module ,


That's correct. You can select a piece of hierarchy in Scope window and the signals at this level can be selected in Objects Window.

For primitive level signals, you need to change xelab debug level from 'typical' to 'all'.

sim_setting.jpg

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189 Views
Registered: ‎07-30-2019

Re: Monitoring of the intermediate Netlist signals of a Primitive

I am new to VHDL and I am not sure this will work in the VHDL to access the intermediate signal during post-layout simulation

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Scholar drjohnsmith
Scholar
180 Views
Registered: ‎07-09-2009

Re: Monitoring of the intermediate Netlist signals of a Primitive

Go through the tutorial we posted back, and have a play around with the other demos on simulation.

 

As to can you monitor a individual node post synthesis is a good , but mor edetailed question.

 

Remeber, the synthesiser and P&R , all modify your initial design, to keep the same functoinality and meet the timming constraints you set.

Such as , duplication, gate absorbtion, register push back and forward.

 

Its very normal for synthesised design to have very different inside nodes to your thinking,

e.g. think if you made an and / or gate, out of seperate and and or gates. f <= ( A and B ) or ( C and D)

      this you think might would have three gates, and three nodes, but the FPGA will put that into one LUT, inputs ABCD and one output F, so only one node, you willnot be able to probe post synthesis A and B  ,  C and D,  .

 

There are ways around this, you can force the tools not to optimise, but thats very counter productive and I'd say at this point not to use it.

 

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