I am seeing with a few issues with the Vivado simulator. I have a VHDL design an at times I am finding that if I make changes to the design, such as add another port to an entity, that the simulator doesnt pick up the changes. It just has the signal as U. If I then close the project and delete the sim dir then start it back up, everything works fine. I am also seeing issues with if I restart the simulator then Vivado just suddenly crashes. I see this maybe 4 or 5 times per day. Does Xilinx know what is causing these issues?