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beandigital
Scholar
Scholar
274 Views
Registered: ‎04-27-2010

Multiple issues with Vivado 2020.1 sim

I am seeing with a few issues with the Vivado simulator. I have a VHDL design an at times I am finding that if I make changes to the design, such as add another port to an entity, that the simulator doesnt pick up the changes. It just has the signal as U. If I then close the project and delete the sim dir then start it back up, everything works fine. I am also seeing issues with if I restart the simulator then Vivado just suddenly crashes. I see this maybe 4 or 5 times per day. Does Xilinx know what is causing these issues? 

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miti
Xilinx Employee
Xilinx Employee
250 Views
Registered: ‎06-10-2020

1. After updating the source files please use laucnh_simulation, it should take all the changes.

2. Can you let us know which vivado version/ OS you are using, if possible please share the project /testcase here.

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