04-17-2020 07:44 AM
I have BASYS 3 with artix 7 fpga.
this is my testbench code:
entity tb_TimerxCounter is
architecture tb of tb_TimerxCounter is
port (Clock_in : in std_logic;
Clock_out_1kHz : out std_logic;
Clock_out_1Hz : out std_logic);
signal Clock_in : std_logic;
signal Clock_out_1kHz : std_logic;
signal Clock_out_1Hz : std_logic;
dut : TimerxCounter
port map (Clock_in => Clock_in,
Clock_out_1kHz => Clock_out_1kHz,
Clock_out_1Hz => Clock_out_1Hz);
stimuli : process
-- EDIT Adapt initialization as needed
Clock_in <= '0';
-- EDIT Add stimuli here
Clock_in <= not Clock_in after 100 ns;
-- Configuration block below is required by some simulators. Usually no need to edit.
configuration cfg_tb_TimerxCounter of tb_TimerxCounter is
But when i run Behavioral simulation, It takes forever!!! plz help i can't do anything with it...
04-17-2020 07:51 AM
What is the time increment on your simulation? I think most simulators are defaulting to 1pS. If you change this to 1nS, the simulation will run faster. Be aware that many Xilinx primitives need to be run with a 1pS simulation time increment, so this may only work on simple simulations.
07-20-2020 05:52 PM
Hi @zaahm18 ,
Can you please share the test case to check this issue at our end? Also which version of Vivado are you using?