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akshath@13
Visitor
Visitor
2,135 Views
Registered: ‎06-26-2017

Netlist Simulation Consuming lot of RAM and Memory

Hello,

I am trying to simulate one netlist for 7v2000tflg1925-2 device. The size of netlist is 695MB.

During elaboration phase the vivado simulator takes around 55 GB RAM along with that it will also take 190GB of Physical Memory.

Here is the resource utilization:

Slice LUT 54%

Slice Register 18%

BRAM 41%

.

Is this behavior is expected? or whether we are missing something??

 

Regards,

Akshath Kumar

 

 

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muzaffer
Teacher
Teacher
2,074 Views
Registered: ‎03-31-2012

akshath@13 unfortunately this is the nature of the beast ie netlist (gate-level) simulations consume more memory and run more slowly than RTL simulations. Xilinx simulators are especially not optimized for this case (maybe they think you can just program the chip and try as it's "field programmable" ?). You might try a different simulator which is more expensive but uses less memory and runs faster.

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