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2,143 Views
Registered: ‎01-15-2018

Netlist Simulation Error :

Hi,

 

I am trying to compile a simple memory controller design in vcs with unisims dir as library. I am running into these three errors. Appreciate help. I am not using Vivado generated scripts. I tried with DDR4 controller as well as with xDMA, two separate runs, both run into same error. 

 

Is there any library am I missing to add? I could not find SIP*.. module in Vivado installation directory. 

 

Appreciate help.

 

Regards,

Shreyas 

 

 

 

 

 

Error-[URMI] Unresolved modules
/home/cad/tools/xilinx/Vivado/LATEST/data/verilog/src/unisims/GTHE3_CHANNEL.v, 3726
"SIP_GTHE3_CHANNEL #(.SIM_RECEIVER_DETECT_PASS(SIM_RECEIVER_DETECT_PASS_REG), .SIM_RESET_SPEEDUP(SIM_RESET_SPEEDUP_REG),

.SIM_TX_EIDLE_DRIVE_LEVEL(SIM_TX_EIDLE_DRIVE_LEVEL_REG), .SIM_VERSION(SIM_VERSION_REG)) SIP_GTHE3_CHANNEL_INST( .ACJTAG_DEBUG_MODE (ACJTAG_DEBUG_MODE_REG), .ACJTAG_MODE 

 

Error-[URMI] Unresolved modules
/home/cad/tools/xilinx/Vivado/LATEST/data/verilog/src/unisims/GTHE3_COMMON.v, 759
"SIP_GTHE3_COMMON #(.SIM_RESET_SPEEDUP(SIM_RESET_SPEEDUP_REG), .SIM_VERSION(SIM_VERSION_REG)) SIP_GTHE3_COMMON_INST( .AEN_BGBS0 (AEN_BGBS0_REG), .AEN_BGBS1 (AEN_BGBS1_REG), .AEN_MASTER0

 

Error-[URMI] Unresolved modules
/home/cad/tools/xilinx/Vivado/LATEST/data/verilog/src/unisims/PCIE_3_1.v, 8089
"SIP_PCIE_3_1 #(.MCAP_ENABLE_PAR(MCAP_ENABLE), .SIM_JTAG_IDCODE(SIM_JTAG_IDCODE)) SIP_PCIE_3_1_INST( .ARI_CAP_ENABLE (ARI_CAP_ENABLE_REG), .AXISTEN_IF_CC_ALIGNMENT_MODE (AXISTEN_IF_CC_ALIGNMENT_MODE_REG), .AXISTEN_IF_CC_PARITY_CHK (AXISTEN_IF_CC_PARITY_CHK_REG),

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17 Replies
Moderator
Moderator
2,129 Views
Registered: ‎09-15-2016

Re: Netlist Simulation Error :

Hi sshah@esperantotech.com

 

Which Vivado version you are using and what is VCS version? Firstly you need to make sure that you are using supported VCS version with the Vivado version you are using. With Vivado 2017.4, the supported VCS version is mentioned in the below link, page 11:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug973-vivado-release-notes-install-license.pdf

 

Also were you able to compile the unisim libraries successfully using the below command or in the Vivado GUI? Are there any errors or warnings?

compile_simlib -simulator vcs -simulator_exec_path <> -family all -language all -library unisim -dir {<project_path>/my_project.cache/compile_simlib}

 

Could you try scripts created by Vivado using export_simulation command, run in VCS and let us know if you are facing similar errors? Refer UG900 for info on the command.

 

Regards

Rohit

 

Regards
Rohit
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2,114 Views
Registered: ‎01-15-2018

Re: Netlist Simulation Error :

Hi I ran the command you mentioned in tcl window. it went through... 

 

compile_simlib -simulator vcs -family all -language all -library unisim -dir {<project_path>/my_project.cache/compile_simlib}

 

I see new directories created under /project.cache/compile_simlib/vcs ... there are no files in the directory. 

 

Regards,

Shreyas

 

 

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2,111 Views
Registered: ‎01-15-2018

Re: Netlist Simulation Error :

Forgot to mention, it can not find synopsys_sim.setup file. 

 

 

 

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2,100 Views
Registered: ‎01-15-2018

Re: Netlist Simulation Error :

This is the error I get during compilation

 

Boost: File_system: copy_file : No such file or directory "synopsys_sim.setup", /home... project.cache/compile_simlib/synopsys_sim.setup

 

I copied synopsys_sim.setup from my xilinx directory to project.cache ... still same error as above.

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Xilinx Employee
Xilinx Employee
2,065 Views
Registered: ‎09-25-2014

Re: Netlist Simulation Error :

Hi sshah@esperantotech.com,

 

" ran the command you mentioned in tcl window. it went through... 

 

compile_simlib -simulator vcs -family all -language all -library unisim -dir {<project_path>/my_project.cache/compile_simlib}"

 

Did you see any errors in the compile_simlib.log which gets generated when you run this command?

 

Thanks,

Srimayee

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2,057 Views
Registered: ‎01-15-2018

Re: Netlist Simulation Error :

Hi Srimayee,

 

yes, I notice the two errors  repeated in logfile.

 

Error: can not update non-existent setup file synopsys_sim.setup

Error: Failed to update the setup file for simulator vcs_mx. Library verilog.secureip will not be compiled. 

 

I copied my synopsys_sim.setup from xilinx directory to project.cache directory, it did not help. 

 

Regards,

Shreyas

 

 

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Xilinx Employee
Xilinx Employee
2,049 Views
Registered: ‎09-25-2014

Re: Netlist Simulation Error :

Hi sshah@esperantotech.com,

 

Can you try by giving the executable path explicitly :

 

compile_simlib -simulator vcs -family all -language all  -library unisim -dir {<project_path>/my_project.cache/compile_simlib}  -simulator_exec_path {<vcs executable path till your bin>}

 

Thanks,

Srimayee

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2,028 Views
Registered: ‎01-15-2018

Re: Netlist Simulation Error :

Explicit path does not work, it appends with my project path and try to find vcs in that dir, e.g. 

/home/eng/sshah/home/cad/tools/snps ... not found. 

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Highlighted
Xilinx Employee
Xilinx Employee
2,021 Views
Registered: ‎09-25-2014

Re: Netlist Simulation Error :

That is not expected. Which OS are you using?

 

Thanks,

Srimayee

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1,636 Views
Registered: ‎01-15-2018

Re: Netlist Simulation Error :

Hi Srimaye,

 

I use Centos 7.2

 

Regards,

Shreyas

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Moderator
Moderator
1,611 Views
Registered: ‎05-31-2017

Re: Netlist Simulation Error :

Hi sshah@esperantotech.com,

 

Have you tried  copying the "Synopsys_sim.setup" file from the Synopsis installation directory to the current working directory, then try to compile the simulation libraries and check if it helps.

 

 

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1,592 Views
Registered: ‎01-15-2018

Re: Netlist Simulation Error :

here is the log. higher level question, is vcs_mx supported 3rd party tool to compile sim_lib? 

 

 

1. By explicitly specifying the path for vcs.. it gave me error. tried different variants, e.g. removed the link (LATEST) to explicit path to N-12... etc .. did not help.

2. i tried without specifying the explicit path

 

ERROR: [Vivado 12-5500] Simulator executable path specified with the -simulator_exec_path switch does not exist! '/home/cad/tools/snps/vcs/N-2017.12-1//bin/ '

 

This log is for without specifying the explicit path 

 


compile_simlib -simulator vcs -family all -language all -library unisim -dir {/home/eng/sshah/Test/Test.cache/compile_simlib}
INFO: [Vivado 12-4753] Extracting data from the IP repository...(this may take a while, please wait)...

INFO: [setup_ip_static_library-Tcl-23] Data extracted from repository. Inspected 393 IP libraries.

INFO: [Vivado 12-5496] Finding simulator executables and checking version...
INFO: [Vivado 12-5498] Processing source library information for the selected device family (default:all) ...

Compiling libraries for 'vcs_mx' in '/home/eng/sshah/Test/Test.cache/compile_simlib'

Compiling verilog library 'secureip'...
compile_simlib: 2 error(s), 2 warning(s), 0.30 % complete

Compiling vhdl library 'unisim'...execve failed: No such file or directory

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Moderator
Moderator
1,578 Views
Registered: ‎09-15-2016

Re: Netlist Simulation Error :

Hi sshah@esperantotech.com

 

I guess the error below could be caused because of the use of unsupported characters in the directory names[hyphen(-) and backslash(/)]

ERROR: [Vivado 12-5500] Simulator executable path specified with the -simulator_exec_path switch does not exist! '/home/cad/tools/snps/vcs/N-2017.12-1//bin/ '

 

Could you rename the directory paths with supported characters as per below link, Appendix B and specify the path explicitly while running compile_simlib command?

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug895-vivado-system-level-design-entry.pdf

 

Regards

Rohit

 

Regards
Rohit
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1,566 Views
Registered: ‎01-15-2018

Re: Netlist Simulation Error :

Thanks Rohit, I am trying based on your suggestion.. will let you know.

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1,561 Views
Registered: ‎01-15-2018

Re: Netlist Simulation Error :

i created a link in my home directory for vcs, changed language to verilog. 

 

It can not find vhdl library.

 

compile_simlib -simulator vcs -family all -language verilog -library unisim -dir {/home/eng/sshah/Test/Test.cache/compile_simlib} -simulator_exec_path {/home/eng/sshah/}
WARNING: [Vivado 12-5377] Language specific library compilation for IPs is not supported. By default, the libraries will be compiled for all languages.
INFO: [Vivado 12-4753] Extracting data from the IP repository...(this may take a while, please wait)...

INFO: [setup_ip_static_library-Tcl-23] Data extracted from repository. Inspected 393 IP libraries.

INFO: [Vivado 12-5496] Finding simulator executables and checking version...
INFO: [Vivado 12-5498] Processing source library information for the selected device family (default:all) ...

Compiling libraries for 'vcs_mx' in '/home/eng/sshah/Test/Test.cache/compile_simlib'

Compiling verilog library 'secureip'...
compile_simlib: 2 error(s), 2 warning(s), 0.30 % complete

Compiling vhdl library 'unisim'...execve failed: No such file or directory

 

 

 

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1,521 Views
Registered: ‎01-15-2018

Re: Netlist Simulation Error :

i am using Centos 7.0. 

 

Regards,

Shreyas

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Newbie ckmufeng
Newbie
1,144 Views
Registered: ‎05-14-2018

Re: Netlist Simulation Error :

I meet the same error!

i add the "-f $(XILINX_VIVADO/data/secureip/secureip_cell.list.f" to the vcs makefile.

the error disappear。 

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