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w18kev
Newbie
Newbie
1,648 Views
Registered: ‎11-28-2017

Newbie - Stuck and in need of some help - VHDL simulation using XiLinx (error:HDLCompiler:806)

Hi All,

 

I am a uni student, designing a vending machine. I am trying to simulate it in VHDL using Xilinx.

 

I have errors on all the lines with a new state (S1/S2/S3/S4).

 

Can anyone see why? Im struggling here!

 

Many thanks in advance :)

 

Code is attached.

 

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6 Replies
u4223374
Advisor
Advisor
1,633 Views
Registered: ‎04-26-2015

Please tell me that you're not writing VHDL code in Microsoft Word...

 

Can you post what the errors are?

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florentw
Moderator
Moderator
1,627 Views
Registered: ‎11-09-2015

Hi @w18kev,

 

You are a newbie so here are some rules you might want to follow on the forum (which should help you to get a better help):

  • "Newbie - Stuck and in need of some help :)" - this is not a good title for a post on the forum. You should describe your issue in the title. This way, if somebody knows he can see from the title if he can help you or not. Not everybody wants to read everypost (I would even say nobody). Here it should have at least contained VHDL and maybe the error message you have
  • You post is not in the correct forum. If you had the error message after synthesis, if should be under synthesis
  • You are not describing your issue. Same, as @u4223374 mentioned, nobody likes reading someone else's code. Paste the error message / a screenshot of vivado. Then post your code attached for reference (if somebody knows he will read the codee to find what could be wrong)

To conclude: Do not expect the forum to do everything for you. The forum is here to assist you, not do all the work for you.

 

Give more information and you will get more help

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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shameera
Moderator
Moderator
1,605 Views
Registered: ‎05-31-2017

Hi @w18kev,

As, you are a newbie. Please make sure that you follow the suggestions of @florentw so that you can get quick support from the forum.

Regarding this post, the issue is with the syntax of the code where you have used else if rather than elsif which was showing errors at (S1/S2/S3/S4). Here, I have attached the modified VHDL file for your reference.

 

Thanks & Regards,

A.Shameer.

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w18kev
Newbie
Newbie
1,604 Views
Registered: ‎11-28-2017

Thanks for the constructive feedback.

 

The code was written using ISE design suite 14.6 and I copied it into word to attach to this forum.

 

When I perform 'behavioral check syntax' I get ERROR:HDLCompiler:806. I have attached a screenshot of the error message and I have highlighted the first line with the error.

 

Many thanks in advance.

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dpaul24
Scholar
Scholar
1,575 Views
Registered: ‎08-07-2014

@w18kev,

 

You are having a syntax error and it is shown by ISE.

when s1 => ;

Syntax errors are simple enough to be searched out and resolved by the code-writer.

 

Just use the code given above from sameera - fsm_for.vhd ‏2 KB

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w18kev
Newbie
Newbie
1,565 Views
Registered: ‎11-28-2017

Thank you very much!

 

All help and assistance well received and appreciated.

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