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Visitor wblee
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1,093 Views
Registered: ‎02-23-2018

On-Chip Verification of AXI-Stream Modules

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Greetings,

 

I'm currently in the process of development with 7 Series FPGAs and am formulating simulation and verification methods for my company.  I'm looking to test AXI-Stream modules alone on the FPGA directly and in an automated fashion.  I'd like to provide a set of input vectors, record the output vectors and compare the outputs with the simulation and model outputs.  What is the most elegant method to achieve this?

 

A little more about what we're trying to do:

         1) Generate input vectors to test an AXI-Stream module in Python (Done)

         2) Send input into a high level model (C, Matlab, Python, etc.)   (Done)

         3) Perform an RTL simulation using the same input vectors, record the output. (Done)

         4) Implement the module into an on-chip testbench, provide the same input vectors,

             record the output (???)

 

For input to the modules, the VIO IP core seems to be only very low speed transactions, and as far as I've seen it's not really equipped to provide a large set of input vectors, rather it's meant to just toggle low-speed I/Os. 

 

As of right now, I'm considering just writing a module that will take the input vectors from a block ram, initialized with a .COE file containing the data, then send these input vectors into the AXI-Stream module.  On the output, I'd use an ILA or System ILA to record the traffic to a .CSV file and then process the .CSV file with Python.  This seems like a rather tedious way to do this and I suspect there might be a much more elegant solution I just don't know about. 

 

Are any of you aware of what is the best and most elegant way to simulate invidual AXI-Stream modules directly on the FPGA with arbitrarily defined input vectors?  Thanks in advance.

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Scholar hbucher
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1,421 Views
Registered: ‎03-22-2016

Re: On-Chip Verification of AXI-Stream Modules

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@wblee It does not apply to SoC only. It applies to Microblaze too.

Add one Microblaze and DMA your stream from/to memory, perhaps BRAM. Apply XSCT method.

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Scholar hbucher
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Registered: ‎03-22-2016

Re: On-Chip Verification of AXI-Stream Modules

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@wblee you could script-push data to fpga memory with XSCT mwr command.  

 

Read 100 words from binary file mem.bin and write the data at target address 0x0.

mwr -bin -file mem.bin 0 100

 Then read it back

Read 100 words at address 0x0 and write the binary data to mem.bin

mrd -bin -file mem.bin 0 100

https://www.xilinx.com/html_docs/xilinx2017_4/SDK_Doc/xsct/memory/reference_memory_mwr.html

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Visitor wblee
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Registered: ‎02-23-2018

Re: On-Chip Verification of AXI-Stream Modules

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hbucher,

 

thank you for the reply, but I'm not sure that applies to what I'm talking about.  The XCST tool applies to SoCs using the SDK, not with 7 Series FPGAs, and when dealing with a sole AXI-Stream module we don't have a memory-mapped address space, so memory reads and writes in this context don't apply.

 

I'm looking for a general method to hardware test FPGA modules on the hardware directly and compare it with the simulation results.  In the OP I described what I'm considering doing, but I feel like that is a better way to do it as this is a very common thing that needs to be tested.

 

If anyone else knows of a good way to test FPGA modules directly on the FPGA, with data blocks in and out, please let me know.

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Scholar hbucher
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1,422 Views
Registered: ‎03-22-2016

Re: On-Chip Verification of AXI-Stream Modules

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@wblee It does not apply to SoC only. It applies to Microblaze too.

Add one Microblaze and DMA your stream from/to memory, perhaps BRAM. Apply XSCT method.

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Visitor wblee
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Registered: ‎02-23-2018

Re: On-Chip Verification of AXI-Stream Modules

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I've looked more into this and was able to try it out.  This is actually a pretty good answer.  Thank you, hbucher!