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Newbie guelm
Newbie
6,991 Views
Registered: ‎02-03-2016

Order of operands in simple signed addition

I have a very simple,combinational signed addition component. Code is below;

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;



entity adder is
    Port ( op1 : in  signed (31 downto 0);
           op2 : in  signed (31 downto 0);
           res : out  signed (31 downto 0));
end adder;

architecture RTL of adder is

begin

res <= op1 + op2;

end RTL;

When simulating, I observe a very peculiar behavior. If I assign values as :

 

op2<=X"00000000";
op1<=X"11111111";

I get the correct result; res = X"11111111"

 

However,when operands are changed so that 

op1<=X"00000000";
op2<=X"11111111";

 

I get a completely different value; res = X"eeeeeeef", which is the correct result but signed conversion applied. Why does order of operands matter, or is this some sort of bug on the tool, since I use last version of ISim on Windows 10.

 

Thanks!

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2 Replies
Xilinx Employee
Xilinx Employee
6,953 Views
Registered: ‎08-02-2011

Re: Order of operands in simple signed addition

Hello,

Can you post a screenshot of the simulation waveform for both cases and snippet of your TB driving op1/op2?
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Newbie guelm
Newbie
6,938 Views
Registered: ‎02-03-2016

Re: Order of operands in simple signed addition

Here is the testbench;

 

 LIBRARY ieee;
  USE ieee.std_logic_1164.ALL;
  USE ieee.numeric_std.ALL;

  ENTITY adder_tb IS
  END adder_tb;

  ARCHITECTURE behavior OF adder_tb IS 

  -- Component Declaration
          component adder 
			 Port ( op1 : in  signed (31 downto 0);
           op2 : in  signed (31 downto 0);
           res : out  signed (31 downto 0));
end component;

          
          SIGNAL op1 :  signed(31 downto 0);
			 SIGNAL op2 :  signed(31 downto 0);
			 SIGNAL res :  signed(31 downto 0);
          

  BEGIN

  -- Component Instantiation
          uut: adder PORT MAP(
                  op1 => op1,op2=>op2,res=>res
          );


  --  Test Bench Statements
     tb : PROCESS
     BEGIN

        op2<=X"00000000";
		  op1<=X"11111111";
		  wait ;
		end process;
  --  End Test Bench 

  END;

Here are the screenshots;

 

correct.JPG

 

wrong.JPG

 

Thanks!

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