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- Output of Floating Point IP result tvalid is 'X'

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wyatt_ogden

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03-24-2019 03:18 AM - edited 03-24-2019 12:25 PM

731 Views

Registered:
01-13-2019

Output of Floating Point IP result tvalid is 'X'

Hey everyone,

I'm trying to get a simple testbench for the floating point IP to work to see how I can integrate it into my own, but I seem to be having some problems.

NOTE: I cut out the answer in the screen shot :(. But it does in fact return 01! Which is expected

Here is the waveform image. I simply compare the value of 10 with 10 and perform an is == operation. The answer seems to be correct but for some reason the tvalid signal is showing up as undefined instead of as a logical high as stated in the data sheet.

Here's the test bench I'm driving with.

module fp_tb( ); reg [31:0]M_AXIS_A_tdata_tb; reg M_AXIS_A_tvalid_tb; reg [31:0]M_AXIS_B_tdata_tb; reg M_AXIS_B_tvalid_tb; reg [7:0]M_AXIS_OPERATION_tdata_tb; reg M_AXIS_OPERATION_tvalid_tb; wire [7:0]M_AXIS_RESULT_tdata_tb; wire M_AXIS_RESULT_tvalid_tb; reg aclk_tb; reg aclken_tb; reg aresetn_tb; fp_design_wrapper DUT ( .S_AXIS_A_tdata(M_AXIS_A_tdata_tb), .S_AXIS_B_tdata(M_AXIS_B_tdata_tb), .S_AXIS_B_tvalid(M_AXIS_B_tvalid_tb), .S_AXIS_OPERATION_tdata(M_AXIS_OPERATION_tdata_tb), .S_AXIS_OPERATION_tvalid(M_AXIS_OPERATION_tvalid_tb), .M_AXIS_RESULT_tdata(M_AXIS_RESULT_tdata_tb), .M_AXIS_RESULT_tvalid(M_AXIS_RESULT_tvalid_tb), .aclk(aclk_tb), .aclken(aclken_tb), .aresetn(aresetn_tb) ); task clk_tick; begin aclk_tb = 0; #1; aclk_tb = 1; #1; end endtask initial begin aresetn_tb =0; M_AXIS_A_tdata_tb = 0; M_AXIS_B_tdata_tb = 0; M_AXIS_A_tvalid_tb = 0; M_AXIS_B_tvalid_tb = 0; M_AXIS_OPERATION_tvalid_tb = 0; M_AXIS_OPERATION_tdata_tb = 1; clk_tick;clk_tick;clk_tick;clk_tick;clk_tick;clk_tick;clk_tick;clk_tick;clk_tick; clk_tick;clk_tick;clk_tick;clk_tick;clk_tick;clk_tick;clk_tick;clk_tick;clk_tick; aresetn_tb = 1; clk_tick; clk_tick; aclken_tb = 1; clk_tick; M_AXIS_A_tdata_tb = 32'h0x41200000; M_AXIS_B_tdata_tb = 32'h0x41200000; M_AXIS_A_tvalid_tb = 1'b1; M_AXIS_B_tvalid_tb = 1'b1; M_AXIS_OPERATION_tvalid_tb = 1; M_AXIS_OPERATION_tdata_tb = 8'b010100; while(1)begin clk_tick; end aresetn_tb = 0; clk_tick; clk_tick; clk_tick; end endmodule

I've also tried this same test with the addition module and cannot get result_tvalid to go high instead of undefined.

What's going on here?

2 Replies

bandi

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04-08-2019 01:55 AM

612 Views

Registered:
09-15-2016

Hi @wyatt_ogden,

Can you please share the archived project with the .xci file to check at our end.

Thanks & Regards,

Sravanthi B

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Sravanthi B

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andrewlan

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04-08-2019 04:57 AM

599 Views

Registered:
06-25-2014