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Registered: ‎10-13-2017

Outputs of module having unknown logic values

Hey everyone, I don't know why my outputs keep having unknown values. I'm building a circuit that carries out the Collatz procedure; it keeps going on if there is no overflow or the input isn't 1. I've tested the combinational block and it works fine. In the combinational module, end and over are declared as outputs. So, I've instantiated an instance of that in my sequential module. This time though I want the output of my sequential block to output the sequence of computation once it terminates. But I still want the outputs of end and over to display in my sequential output and I'm having trouble getting this right. I've tried declaring it as both reg and wire, but nothing comes up on my outputs. Here is my code:

 

module collatz_sequential(
    input [7:0] X,
    input Clock,
    input Start,
    output [7:0] C,
    output End,
    output over
    );
    
    wire [7:0] driver;
    wire [7:0] selected;
    wire [7:0] out;
    wire signal_end, signal_over;
    reg END, OVER;
    reg [7:0] C = 8'b00000001;
    wire start;
    reg startn;
    wire clrn = 1;
    
    assign start = Start;
    
    assign signal_end = End;
    assign signal_ = over;
    
    always@(*)begin
    assign END = signal_end;
    assign OVER = signal_over;end
    assign clrn = ~( END | OVER ) | start;
    
    parameter reset = 0, processing = 1;
    reg state = reset, nextState;
   
    mux_8bit input_select (out, X, start, selected);
    parallel_8bit_reg register (selected, Clock, clrn, driver);
    collatz_comb comb_Part (driver, out, End, over);
    
    always@(*)begin
    if ( END || OVER )begin
    nextState = reset;end
    else if (start)begin
    nextState = processing;end
    end
    
    always@(posedge Clock)begin
    state <= nextState;
    if ( state == processing )begin
    C = C + 1'd1;end
    end
    
    always@(negedge Clock)begin
    if(start)begin
    startn = 0;end
    end
 
    assign start = startn;
    
endmodule

Any thoughts? I'm new to FSM too so is it an error elsewhere? Thanks!

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Registered: ‎11-09-2015

Re: Outputs of module having unknown logic values

Hi @limxx518,

 

Just looking at the output "End". You are never giving it a values. The only thing that you are doing is reading it:

assign signal_end = End;

Why did you declare it as output if you are reading it? It should be an input...

 

Re-do your FSM step by step and it will work if you are careful...

 

Regards,

 

Florent


Florent
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Registered: ‎10-13-2017

Re: Outputs of module having unknown logic values

Hi @florentw, thanks for your reply! I want to read it and output it as well. So End should be the output from my collatz_comb module. And if end or over isn't zero, I would want the output from the collatz_comb module to be computed again. However, if end or over is zero, I want to feed the outputs of the collatz_comb module to the outputs of my sequential module.

That's why you see that End and over in the instantiation module of collatz_comb is the same as the outputs in my sequential module. Is it possible to do that?

Since I also want to read the outputs of the comb circuit to determine the state of my FSM, I declared END and OVER as regs, since they are the data type that can store values.

 

I've included a pic of the description to make it clearer

TLDR; I want end and over to be outputs as well as values that can be read to determine next states of FSM.

colatz.JPG
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Registered: ‎11-09-2015

Re: Outputs of module having unknown logic values

Hi @limxx518,

 

That's why you see that End and over in the instantiation module of collatz_comb is the same as the outputs in my sequential module. Is it possible to do that?

I don't really know for verilog. You should create a wire it should be clearer.

 

You might want to show what your waveform looks like.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎10-13-2017

Re: Outputs of module having unknown logic values

Hi @florentw, so I've did as you suggested, namely I assigned the outputs of the comb module to a wire instead. It still isn't working though. Here are the assignment changes I made:

 

EDIT 1: I realise I can't assign that as a wire, for I can't read values from a wire, can I? It seems that the implementation of my FSM needs to be changed.

 

EDIT 2: No,  I think it will work if I assign values of signal_end and signal_over to reg values END and OVER in an always statement. I did that but the simulation results remain the same. Puzzling.

wire signal_end, signal_over;

assign End = signal_end;
assign over = signal_over;

collatz_comb comb_Part (driver, out, signal_end, signal_over);

Here is the testbench file:

module collatz_sequential_tb(

    );
    
    reg [7:0] X;
    reg Clock;
    reg Start;
    
    wire [7:0] C;
    wire End;
    wire over;
    
    collatz_sequential DUT(
    .X(X),
    .Clock(Clock),
    .Start(Start),
    .C(C),
    .End(End),
    .over(over));
    
    initial begin
    Clock = 0;
    X = 3'd5; Start = 1; 
   forever begin
   #20 Clock = ~Clock;
   end 
    X = 3'd 24; Start = 1;
    end
endmodule

Just 2 test cases; I'm not sure if I've written the test bench file correctly though, but the clock seems to work. Here is a screenshot of my behavioral simulation:

collatz_sim.JPG

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Registered: ‎10-13-2017

Re: Outputs of module having unknown logic values

Hi @florentw

I've did as you suggested, namely assigning outputs of comb_module to wires:

wire signal_end, signal_over;

assign End = signal_end;
assign over = signal_over;

reg END, OVER;

always@(*)begin
assign END = signal_end;
assign OVER = signal_over;end

collatz_comb comb_Part(driver, out, signal_end, signal_over);

Reg values are declared as well since I need to read them.

 

Here is my testbench:

module collatz_sequential_tb(

    );
    
    reg [7:0] X;
    reg Clock;
    reg Start;
    
    wire [7:0] C;
    wire End;
    wire over;
    
    collatz_sequential DUT(
    .X(X),
    .Clock(Clock),
    .Start(Start),
    .C(C),
    .End(End),
    .over(over));
    
    initial begin
    Clock = 0;
    X = 3'd5; Start = 1; 
   forever begin
   #20 Clock = ~Clock;
   end 
    X = 3'd 24; Start = 1;
    end
endmodule 

 My testbench has two cases and nothing shows up on my end and over signals. Is my implementation of the FSM feasible? 

Here is my behavioral simulation results:

collatz_sim.JPG

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Registered: ‎11-09-2015

Re: Outputs of module having unknown logic values

Hi @limxx518,

 

You might need to investigate. Try to add internal signals to the waveform.

 

Did you try to do a test bench only for  collatz_comb?

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎10-13-2017

Re: Outputs of module having unknown logic values

Hi @florentw,

Thanks for your hints. Can you elaborate on what it means to add internal signals to the waveform?

Yes I did, and it works.
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Registered: ‎11-09-2015

Re: Outputs of module having unknown logic values

Hi @limxx518,

 

Can you elaborate on what it means to add internal signals to the waveform

> In the object window, you can go deep into your design to see internal signal. You can right click on them and click add to waveform.

 

Yes I did, and it works.

So it is works, how do you explain that the signal End is still unknown. It should be the output of this block

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Re: Outputs of module having unknown logic values

collatz_comb.JPG

Well, it works, the simulation results are above.

 

I've tried adding the internal signals, but it seems that End and over themselves are the internal signals since they are declared as  wires in the testbench. Do you mean using such stuff as $display commands to display values of signal_end and signal_over?

 

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Re: Outputs of module having unknown logic values

Hi @limxx518,

 

Do you mean using such stuff as $display commands to display values of signal_end and signal_over?

No, I mean just finding the signals and add them to the waveform...

 

You might want to follow the simulation tutorial UG937. It will help.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Re: Outputs of module having unknown logic values

EDIT: Ignore this post, I'll try debugging it on my own. Thanks for all your help so far!

 

Hi @florentw, thanks for the manual! It was of great help. I realized the error. It was the way in which I was declaring the inner connections when instantiating the submodules within this sequential module. Also, I realized that I need to provide structural verilog code for this problem, and I think I used behavioral code previously. So, I've made huge changes to my sequential module. Now, a different error comes up, and one in which Vivado doesn't tell me the cause. Firstly, here is my new code for the module:

 

module collatz_sequential(
    input [7:0] X,
    input Clock,
    input Start,
    output [7:0] C,
    output End,
    output over
    );
    
    wire signal_end = 0, signal_over = 0;
    
    wire clock; //clock signal for counter
    assign clock = ~(signal_end | signal_over) & Clock;
    
    wire startbar = 0;
    DFF startn (.D(Start ^ startbar), .Q(startbar), .Clock(Clock), .ClearN(1'b1));
    assign Start = startbar;
    
    wire [7:0] Out;
    assign C = Out;
    
    wire [7:0] selected;
    wire [7:0] Y;
    wire [7:0] Data;
   
    mux_8bit input_select (.X(Y), .Y(X), .Y(startbar), .C(selected));
    parallel_8bit_reg register (.X(selected), .Clock(Clock), .ClearN(1'b1), .Data(Data));
    collatz_comb comb_Part (.X(Data), .Y(Y),.End(signal_End), .over(signal_over));
    binary_counter_8bit counter (.Load(startbar), .Count(1'b1), .Initial(8'b00000001), .Clock(clock), .ClearN(~(End | over)), .Output(C));
    
    assign End = signal_end;
    assign over = signal_over;
    
endmodule

Notice my assignments now have .input(arg) form. I was more confident that things would work this time, since I have a physical design of the circuit, but Vivado wouldn't let me run the behavioral simulation. It gives me this error:

[USF-XSim 62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/xup/digital/2014_2_artix7_labs/Collatz_machine/Collatz_machine.sim/sim_1/behav/xvlog.log' file for more information.

[Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.

There aren't any other messages explaining why the error occurred. I can't find the log file as well despite going to the specified folder. I just managed to find the glbl.v file.

 

Any explanations why this doesn't work? Thanks and sorry for changing the problem.

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Registered: ‎11-09-2015

Re: Outputs of module having unknown logic values

HI @limxx518,

 

I realized the error.

> Good to know. It is better if you find  the issue by yourself. I prefer be here to assist than solve for you.

 

There aren't any other messages explaining why the error occurred. I can't find the log file as well despite going to the specified folder. I just managed to find the glbl.v file. Any explanations why this doesn't work? Thanks and sorry for changing the problem.

> Try again to search for this file. It should be in your project directory under the <project.sim>/behav folder .

This file is generated because there is something wrong with you code (this is a verilog issue).

Alternatively you can look into the tcl console (or log console I can't remember which one). The error message should be displayed.

And if still not, you can try to run synthesis, it might show an issue in your code.

 

Hope that helps,

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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