07-26-2016 04:54 PM
I'm trying to write a SystemVerilog testbench which does something like this:
fork begin // Drive bus master #1 with random commands end begin // Drive bus master #2 with random commands end join
When I do this, each thread receives the same random seed, which is all good -- that's the defined behavior in the LRM. However, I'd like to override that and give each thread a unique random seed so that the two bus masters aren't executing the same sequence.
As far as I can tell, this is how you should set the random seed for the current process in SV:
However, when I try putting one of these in each begin...end block above, XSim errors out with "ERROR: [VRFC 10-91] process is not declared". What am I doing wrong? Or, if XSim doesn't support the 'process' class, is there an alternate way of seeding the RNG per-thread?
p.s. Does Xilinx have any plans to support join_any and join_none? I tried to use join_any and got an error message indicating it isn't supported.
07-26-2016 07:06 PM
Noticed that the LRM says I can give a parameter to $urandom(), and that parameter is used as the random number seed. This seems to work for making my forked threads generate different command sequences.