UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Observer stmilch
Observer
7,158 Views
Registered: ‎04-16-2010

PlanAhead: No ram in microblaze simulation

Jump to solution

I have a PlanAhead project with a microblaze in a lower instance. The processor works fine on hardware.

 

When I start a behavioral simulation the processor finds no ram data and steps to all the memory until it stalls at 0x10004. Even having valid data in the .mem files all input to the processor is zero, so I assume that this is interpreted all as nops and explains the behaviour of the processor.

 

I think all the block ram is not in the simulation model. During fuse.exe processing I get the following warnings:

Starting static elaboration
WARNING:HDLCompiler:89 - "C:/Projekte/tt/TT2177/fpga/ccu_pa/ccu_pa.srcs/sources_1/edk/mb77/simulation/behavioral/mb77.vhd" Line 2363: <mb77_microblaze_0_bram_block_wrapper> remains a black-box since it has no binding entity.
WARNING:HDLCompiler:746 - "C:/Applic/Xilinx/14.7/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_lite_ipif_v1_01_a/hdl/vhdl/slave_attachment.vhd" Line 260: Range is empty (null range)
Completed static elaboration
WARNING:Simulator:648 - "C:/Projekte/tt/TT2177/fpga/ccu_pa/ccu_pa.srcs/sources_1/edk/mb77/simulation/behavioral/mb77.vhd" Line 2363. Instance mb77_microblaze_0_bram_block_wrapper is unbound

 

Fuse is called this way:

C:\Applic\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\fuse.exe -intstyle pa -incremental -L work -L proc_sys_reset_v3_00_a -L lmb_v10_v2_00_b -L lmb_bram_if_cntlr_v3_10_c -L microblaze_0_bram_block_elaborate_v1_00_a -L microblaze_v8_50_c -L iomodule_v1_03_a -L proc_common_v3_00_a -L axi_lite_ipif_v1_01_a -L interrupt_control_v2_01_a -L axi_gpio_v1_01_b -L mdm_v2_10_a -L clock_generator_v4_03_a -L clock_generator_0_v4_03_a -L axi_interconnect_v1_06_a -L unisims_ver -L unimacro_ver -L xilinxcorelib_ver -L secureip -o TestCcuMb.exe --prj C:/Projekte/tt/TT2177/fpga/ccu_pa/ccu_pa.sim/sim_1/behav/TestCcuMb.prj -top work.TestCcuMb -top work.glbl

 

In the simulation hirarchy I find my microblaze (i_mb77) with its peripherals inclusive ilmb, dlmb, dram_ctrl for instruction and data, but NOT the expected bram_block!

 

microblaze.png

 

Any ideas?

 

Thanks

  Stefan

 

0 Kudos
1 Solution

Accepted Solutions
Observer stmilch
Observer
12,886 Views
Registered: ‎04-16-2010

Re: PlanAhead: No ram in microblaze simulation

Jump to solution

Thanks for your hint.

 

I MANUALLY added the wrapper to my design in the work library and so fuse.exe could bind them.

 

But still this seems to be a strange bug in PlanAhead/ISIM configuration.

View solution in original post

0 Kudos
2 Replies
Xilinx Employee
Xilinx Employee
7,151 Views
Registered: ‎10-24-2013

Re: PlanAhead: No ram in microblaze simulation

Jump to solution
Hi,
Check if this helps.
http://www.xilinx.com/support/answers/34620.html
Thanks,Vijay
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.
0 Kudos
Observer stmilch
Observer
12,887 Views
Registered: ‎04-16-2010

Re: PlanAhead: No ram in microblaze simulation

Jump to solution

Thanks for your hint.

 

I MANUALLY added the wrapper to my design in the work library and so fuse.exe could bind them.

 

But still this seems to be a strange bug in PlanAhead/ISIM configuration.

View solution in original post

0 Kudos