cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Adventurer
Adventurer
7,703 Views
Registered: ‎02-08-2013

Planahead STRUCTURAL Fifo

Jump to solution

Hi,

 

my design uses various FIFO's. I'm trying to do a timing simulation using Planahead 14.6. (Windows x64)

 

Fifo generator documentation says I can generate 'structural' model by selecting it in the Core generator project options. In Planahead it is now 'LogiCore' and there aren't any options - by default (even listed in the wizard summary) it will only generate a 'Behavioural' model.

 

Will I have to call upon some tcl commands to generate the structural models for all my fifos??

 

Cheers.

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Adventurer
Adventurer
11,936 Views
Registered: ‎02-08-2013

Re: Planahead STRUCTURAL Fifo

Jump to solution

I found a shortcut. Instead of setting the ip as top level, follow these steps:

 

  • Synthesize design as normal
  • Open synthesized design and traverse to an instance of the IP in the netlist hierarchy - note the cell/ block name in the properties window
  • enter the followig tcl command: write_vhdl -mode funcsim -cell path/to/block/or/cell/in/netlist C:\ip_name.vhd
  • Now add simulation source and select the generated file

View solution in original post

4 Replies
Highlighted
Xilinx Employee
Xilinx Employee
7,699 Views
Registered: ‎09-20-2012

Re: Planahead STRUCTURAL Fifo

Jump to solution

Hi,

 

Follow the below steps to generate structural model of FIFO core.

 

  • In the GUI, Set IP as Top, run synthesis.
  • After synthesis is complete, you can write out a back annotated simulation model for the IP by running the following commands from the TCL console accessible from the GUI.
    • write_verilog -mode funcsim <corename>.v (for Verilog)
    • write_vhdl -mode funcsim <corename>.vhd (for VHDL)
  • Add the model as a simulation only source for the flow to simulate the IP.

Thanks,
Deepika.
Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
0 Kudos
Highlighted
Adventurer
Adventurer
7,693 Views
Registered: ‎02-08-2013

Re: Planahead STRUCTURAL Fifo

Jump to solution

'Set as top' is greyed out for the IP instances in the hierarchy. the Fifo instance refers to the .xci file in brackets -

like this:

 

  - a_component - my_module - Behavioural (my_module.vhd)

       - BUS_FIFO - custom_fifo_name (custom_fifo_name.xci)

                custom_fifo_name - custom_fifo_name_a (cusom_fifo_name.vhd)

                custom_fifo_name (custom_fifo_name.ngc)

 

Can't set any of those as top.

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
7,676 Views
Registered: ‎07-11-2011

Re: Planahead STRUCTURAL Fifo

Jump to solution

Hi,

 

I think you can write a wrapper with .vho and IP interface alone  in the top level entity, do not include any other modules, and set the wrapper as top level, synthesize and then use write_vhdl command.

 

 

Regards,

Vanitha.

 

 

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented
0 Kudos
Highlighted
Adventurer
Adventurer
11,937 Views
Registered: ‎02-08-2013

Re: Planahead STRUCTURAL Fifo

Jump to solution

I found a shortcut. Instead of setting the ip as top level, follow these steps:

 

  • Synthesize design as normal
  • Open synthesized design and traverse to an instance of the IP in the netlist hierarchy - note the cell/ block name in the properties window
  • enter the followig tcl command: write_vhdl -mode funcsim -cell path/to/block/or/cell/in/netlist C:\ip_name.vhd
  • Now add simulation source and select the generated file

View solution in original post