03-22-2021 01:37 PM
I know this has been brought up many times, but it's getting unbelievably frustrating now. Simulating some basic VHDL '08 structures still doesn't work.
Take for example, the ternary operator in a process (x <= a when cond else b). This still can't be simulated in Vivado, even though, under the hood, this could trivially be interpreted as the equivalent five-line if-then-else construction. Why? This is a one-month intern project to get working, if that. It's pretty inexcusable for an expensive industry-leading tool to not support some 13-year old syntax which doesn't even implement a new feature (it's just if-else in disguise!).
Please sort this out. My studies use VHDL exclusively and this is crippling.
03-22-2021 01:56 PM
This is a one-month intern project to get working, if that.
Xilinx will not move fast, even if they, your time will not be honored.
So get yourself a different simulator and get your work done.....Modelsim, GHDL,....
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03-22-2021 02:05 PM
Yup. Its had better synthesis support than sumulation for a number of years - and is rather strange (I dont say frustrating for me, as I have ActiveHDL with VHDL 2019 support!)
GHDL is free and open source (but does have some 2008 issues), and Intel provide modelsim for free in their webpack (starter edition has low code limit before serious slowdown): https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/model-sim.html
I have heard there may be some improvements in 2021.1, but Im not holding my breath.