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Visitor branden
Visitor
278 Views
Registered: ‎11-02-2018

Possible SystemVerilog Array Assignment Bug using Enumerated Types defined in Packages

Under xsim v2017.4.1 (64-bit), I attempted to assign values to an unpacked array as follows

package tpkg;
	typedef enum { DX_FIRST, DX_SECOND, DX_THIRD, DX_NONE } dx_type_t;
endpackage: tpkg

module top_tb();
	logic [4:0] pi [tpkg::dx_type_t.num()]= '{
		tpkg::DX_SECOND     : '1,
		tpkg::DX_THIRD      : 5'd10,
		tpkg::DX_NONE       : 20,
		default             : 0
	};
endmodule: top_tb

Unfortunately this assigns incorrect values with pi={ 20, 0, 0, 0 } reported after execution.

Alternatively, defining the enumerated value in the module or using the "import" statement as shown below results in the expected assignment: pi={ 0, 0x1f, 10, 20 }

package tpkg;
	typedef enum { DX_FIRST, DX_SECOND, DX_THIRD, DX_NONE } dx_type_t;
endpackage: tpkg

module top_tb();
	import tpkg::*;
	
	logic [4:0] pi [dx_type_t.num()]= '{
		DX_SECOND     : '1,
		DX_THIRD      : 5'd10,
		DX_NONE       : 20,
		default       : 0
	};
endmodule: top_tb

 

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Xilinx Employee
Xilinx Employee
203 Views
Registered: ‎08-10-2015

Re: Possible SystemVerilog Array Assignment Bug using Enumerated Types defined in Packages

Hi @branden,

 

Isuue been reported to factory.

 

Thanks,

Sunilkumar