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8,422 Views
Registered: ‎10-14-2010

Post Implementation Timing Simulation for VHDL

Hi,

 

I have run post implementation timing simulation for xc7a35tcpg236-1 FPGA for the following VHDL code in Vivado 2015.4.

entity test is
Port ( a : in STD_LOGIC;
b : out STD_LOGIC);
end test;

architecture Behavioral of test is

begin

b <= a;

end Behavioral;

 

Constrait file

set_property PACKAGE_PIN V17 [get_ports {a}]
set_property IOSTANDARD LVCMOS33 [get_ports {a}]
set_property PACKAGE_PIN U16 [get_ports {b}]
set_property IOSTANDARD LVCMOS33 [get_ports {b}]

 

The synthesized schematic uses only one IBUF and one OBUF as expected. When I run post implementation timing simulation using the following test bench, the delay due to buffers and interconnect is 3.59ns. However, the timing report shows 7.095ns delay. It seems the simulator does not include the delay of OBUF. I have checked sdf file and netlist and have not found any issue. When I designed the circuit in Verilog the simulation result show 7.093ns, which is very close to the delay reported in the timing report.  Is it a simulator bug or is there a parameter that I have to set?

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity test_tb is
-- Port ( );
end test_tb;

architecture Behavioral of test_tb is
COMPONENT test IS
PORT ( a : in STD_LOGIC;
b : out STD_LOGIC);
END COMPONENT;

SIGNAL a_s, b_s: std_logic;

begin

test1: test PORT MAP (a_s,b_s);

PROCESS
BEGIN
a_s <= '0';
WAIT FOR 400 ns;
a_s <= '1';
WAIT FOR 400 ns;
a_s <= '0';
WAIT;
END PROCESS;

end Behavioral;

 

Regards,

 

Burak

7 Replies
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Xilinx Employee
Xilinx Employee
8,393 Views
Registered: ‎09-25-2014

Re: Post Implementation Timing Simulation for VHDL

Hi Burak,

 

I have checked the design at my end and found the same that the OBUF delay is not being seen. This is a bug in vivado simulator. We will fix this in future release.

 

Thanks,

Srimayee

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8,013 Views
Registered: ‎10-14-2010

Re: Post Implementation Timing Simulation for VHDL

Hi,

 

Thanks for your reply. 

 

When I run the timing simulation for sdfmin (the same circuit in Verilog), the delay is 6.509ns. When I checked the SDF file, delay is 1.3826ns from IBUF, 3.3018ns from OBUF and 1.8267ns from interconnect. So the total is 6.5111ns which is very close to simulation report as expected. Howeveri when I checked the unconstrained paths in timing report for HOLD case, the total delay is 1.880ns, where 1.427ns from logic delay and 0.453ns from interconnect delay. Why the timing report and simulation results differ significantly? Btw, they match for Setup and simulations with sdfmax.

 

Regards,

 

Burak Kelleci

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Visitor
Visitor
237 Views
Registered: ‎10-15-2019

Re: Post Implementation Timing Simulation for VHDL

Dear Sir Srimayee

I am working with Vivado 2019.2.

It seems that the bug is not solved.

Respectfully

Wael Alkakhi

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Visitor
Visitor
204 Views
Registered: ‎10-15-2019

Re: Post Implementation Timing Simulation for VHDL

Hi

I also tried to insert a LUT in the code by writting

a <= not b;

instead of

a<= b;

by comparing the implementation timing simulation and the .sdf file, It shows that the time delay due to LUT is not included in the implementation timing simulation.

 

Respectfully

Wael Alkakhi

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Scholar
Scholar
190 Views
Registered: ‎08-01-2012

Re: Post Implementation Timing Simulation for VHDL

@w_alkakhi 

It is likely that synthesis removed the lut as inversions are free. Trying to "fudge" timing by inserting luts is NOT recommended.

Is there any reason you want to do a post implementation simulation? do you suspect an implementation bug? Most designers now dont both with post-sim or post synth simulations. Its much more efficient to do a functional RTL simulation and provide good timing (XDC) files. If the design meets timing then you can test it on hardware. Netlist simulations are slow and usually are not very useful.

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Visitor
Visitor
184 Views
Registered: ‎10-15-2019

Re: Post Implementation Timing Simulation for VHDL

@richardhead 

@srimaye 

Is it an implementation bug?

or is there any solution to include th time delay due to output buffer and the time delay due last LUT before the buffer in the timing implementation simulation?

 

Respectfully

Wael Alkakhi

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Scholar
Scholar
170 Views
Registered: ‎08-01-2012

Re: Post Implementation Timing Simulation for VHDL

No, this is normal behaviour - it will optimise unless you explicity build it with a lut and tell it to keep it. Using not in code will not be good enough (an inverter is basically free)

Why do you want to delay a signal? have you tried the set_output_delay XDC commands in your timing for your pins?

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