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fpgalab
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Registered: ‎03-05-2019

Post Implementation timing Fails

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Hello All,

I have a design which includes an HLS IP. The design meets all the user specified timing constraints , but it fails Post- Implementation Timing Simulation. The HLS IP is giving out wrong values.Also the Post -Implementation Functional Simulation gives expected results.

What could be the possible reason that a design will fail timing simulation while the design meets the timing constraints?

NB:The timing constraints just specifies the clock period. The same HLS IP when teseted alone gave expected results in Post implementation timing simulation. But when integrated to a larger design caused the above said issue.

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fpgalab
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Registered: ‎03-05-2019

 

 

Looks like the issue was with the Vivado Simulator.

When the code was run on the board it gave expected results.

Same issue was reported earlier :

https://forums.xilinx.com/t5/Simulation-and-Verification/Post-Implementation-timing-simulation-error/td-p/785099

 

https://forums.xilinx.com/t5/Simulation-and-Verification/Incorrect-Timing-Simulation/td-p/637029

 

Hope Xilinx will fix the above said issue.

View solution in original post

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watari
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Registered: ‎06-16-2013

Hi @fpgalab 

 

I guess because your design has some clock domains, there is different result between timing simulation and functional simulation.

Would you make sure clock domain crossing, CDC flip flop and the constraint for CDC ?

 

Best regards,

fpgalab
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Registered: ‎03-05-2019

Theres no CDC.. Everything works with same clock.

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fpgalab
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Registered: ‎03-05-2019

 

It also showed warning during simulation :

 

"Timing violation in scope /NBTop_tb/uut/Pnum/gauss/U0/gaussian_fsub_32nbkb_U1/din0_buf1_reg[4]/TChk153_54807 at time 555521 ps $setuphold (posedge C,posedge D,(0:0:0),(0:0:0),notifier,in_clk_enable_p,in_clk_enable_p,C_dly,D_dly)"

 

 

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fpgalab
Visitor
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952 Views
Registered: ‎03-05-2019

 

 

Looks like the issue was with the Vivado Simulator.

When the code was run on the board it gave expected results.

Same issue was reported earlier :

https://forums.xilinx.com/t5/Simulation-and-Verification/Post-Implementation-timing-simulation-error/td-p/785099

 

https://forums.xilinx.com/t5/Simulation-and-Verification/Incorrect-Timing-Simulation/td-p/637029

 

Hope Xilinx will fix the above said issue.

View solution in original post

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