02-17-2010 03:08 PM
I am simulating a carry chain using the CARRY4 units in the Virtex5 and i do not understand the results.
The VHDL code for instantiating the carry4 unit is the following:
signal carry_out,n_out : std_logic_vector(3 downto 0);
Init <= start; Input <= '0'; S <= "1111"; DI <= "1111"; carry4_line1: CARRY4 port map( CO => carry_out, O => n_out, CI => Input, CYINIT => Init, DI => DI, S=> S );
The signal Init should propagate through the multiplexers and arrive subsequently first at CO(0) then at CO(1) and so on. According to the timing simulation i did with ISim and ModelSim (Libraries from ISE 11.4) the logic transitions that propagates through the line arrives at CO(3) before it arrives at CO(2). I attached the simulation from ModelSim with the signals.
Am i missing something or is this an error in the timing simulation. The output O from the carry4 element is as expected.
Thanks in advance
10-11-2011 02:57 PM
The CARRY4 component incorporates a high speed carry-lookahead circuit inside that speeds up the generation of the last carry bit in order to reduce the delay when these components are chained together. Although the circuit diagram displays the logic as a ripple carry circuit, this lookahead circuit is inside as well.
One thing to note is that the net name in timing simulation is the direct ouptut of the CARRY4 component, prior to the multiplexers and any routing delay to the registers, or slice outputs. If you were to look at the signals at the D inputs of the registers, you would find that the order of arrival for the carry bits is in sequential order from 0 to 3 as you would expect from a ripple carry circuit.
OK, hope this helps,