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Adventurer
Adventurer
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Registered: ‎08-10-2017

Post-Synthesis Simulation for a block design containing AXI VIP

I know this is a silly doubt, and if someone could confirm this, my mind will be at peace

 

Page 38 of AXI Verification IP (https://www.xilinx.com/support/documentation/ip_documentation/axi_vip/v1_0/pg267-axi-vip.pdf) says

Screenshot from 2018-02-07 23-54-10.png

 

Does this mean it is not possible to perform post-synthesis (and by def. post-implementation) simulation for a block design containing a custom AXI IP (having master AXI interface) and AXI VIP IP (having AXI Slave VIP) ?

 

I'm getting this error when I run post-synthesis functional simulation

ERROR: [VRFC 10-93] IF is not declared under prefix inst

Whereas Behavioral Simulation works without any problem.

 

The reason I asked is, I wanted to check if my custom IP is generating correct AXI signals even after I synthesize and implement. 

Is there any way I can quell such concerns ?

(I didn't get any unusual warnings such as sequential element dropped etc. when I synthesized my custom IP in IP Packager)

 

Maybe I'm answering my own questions myself, but I'd like to know if any of above assumptions I've made are incorrect.

 

EDIT 1: 

In case behavioral simulation is sufficient to check if AXI master signals (in custom IP) I'm generating are correct, then can I assume that I won't face any problems (related to AXI) when I include this IP in a larger design ?

 

EDIT 2:

This link  https://forums.xilinx.com/t5/Simulation-and-Verification/Using-AXI-BFM-in-post-synthesis-implementation-simulations/td-p/783671 says that AXI VIP (and BFM) cannot be used for post synthesis and post implementation.

 

Thank You

 

 

Regards

Jagannath

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