Does this mean it is not possible to perform post-synthesis (and by def. post-implementation) simulation for a block design containing a custom AXI IP (having master AXI interface) and AXI VIP IP (having AXI Slave VIP) ?
I'm getting this error when I run post-synthesis functional simulation
ERROR: [VRFC 10-93] IF is not declared under prefix inst
Whereas Behavioral Simulation works without any problem.
The reason I asked is, I wanted to check if my custom IP is generating correct AXI signals even after I synthesize and implement.
Is there any way I can quell such concerns ?
(I didn't get any unusual warnings such as sequential element dropped etc. when I synthesized my custom IP in IP Packager)
Maybe I'm answering my own questions myself, but I'd like to know if any of above assumptions I've made are incorrect.
In case behavioral simulation is sufficient to check if AXI master signals (in custom IP) I'm generating are correct, then can I assume that I won't face any problems (related to AXI) when I include this IP in a larger design ?