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Visitor jclemons
Visitor
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Registered: ‎09-10-2016

Post Synthesis Simulation with VIP in testbench Not Working Vivado 2017.1 Linux

I am using Vivdao 2017.1 on linux.  I can get the behavioral simulation to work.  However, when I try to do a post synthesis simulation I get the following error:

 

Using 8 slave threads.
Starting static elaboration
ERROR: [VRFC 10-2063] Module <axi_vip_0> not found while processing module instance <axi_vip_0_tb_inst> [/home/scratch.jclemons_nvresearch/hls/jclemons-research-scratch-hls/avr/sandbox_rc17/fpga/fpga_host/vivado/Jason_fpga_host_test_sim/Jason_fpga_host_test_sim.srcs/sim_2/new/testbench_postsyn.sv:401]
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.
INFO: [USF-XSim-69] 'elaborate' step finished in '5' seconds

 

 

The testbench looks like

```

import axi_vip_v1_0_1_pkg::*;
//import axi_vip_0_pkg::*;
//import sim_design_1_axi_vip_0_0_pkg::*;
//import axi_vip_0_pkg::*;

module testbench(
);

 

...

axi_vip_0 axi_vip_0_tb_inst (
.aclk(clock), // input wire aclk
.aresetn(reset), // input wire aresetn
.m_axi_awaddr(m_axi_awaddr), // output wire [63 : 0] m_axi_awaddr
.m_axi_awlen(m_axi_awlen), // output wire [7 : 0] m_axi_awlen
.m_axi_awsize(m_axi_awsize), // output wire [2 : 0] m_axi_awsize
.m_axi_awburst(m_axi_awburst), // output wire [1 : 0] m_axi_awburst
.m_axi_awlock(m_axi_awlock), // output wire [0 : 0] m_axi_awlock
.m_axi_awcache(m_axi_awcache), // output wire [3 : 0] m_axi_awcache
.m_axi_awprot(m_axi_awprot), // output wire [2 : 0] m_axi_awprot
.m_axi_awregion(m_axi_awregion), // output wire [3 : 0] m_axi_awregion
.m_axi_awqos(m_axi_awqos), // output wire [3 : 0] m_axi_awqos
.m_axi_awuser(m_axi_awuser), // output wire [2 : 0] m_axi_awuser
.m_axi_awvalid(m_axi_awvalid), // output wire m_axi_awvalid
.m_axi_awready(m_axi_awready), // input wire m_axi_awready
.m_axi_wdata(m_axi_wdata), // output wire [63 : 0] m_axi_wdata
.m_axi_wstrb(m_axi_wstrb), // output wire [7 : 0] m_axi_wstrb
.m_axi_wlast(m_axi_wlast), // output wire m_axi_wlast
.m_axi_wuser(m_axi_wuser), // output wire [2 : 0] m_axi_wuser
.m_axi_wvalid(m_axi_wvalid), // output wire m_axi_wvalid
.m_axi_wready(m_axi_wready), // input wire m_axi_wready
.m_axi_bresp(m_axi_bresp), // input wire [1 : 0] m_axi_bresp
.m_axi_buser(m_axi_buser), // input wire [2 : 0] m_axi_buser
.m_axi_bvalid(m_axi_bvalid), // input wire m_axi_bvalid
.m_axi_bready(m_axi_bready), // output wire m_axi_bready
.m_axi_araddr(m_axi_araddr), // output wire [63 : 0] m_axi_araddr
.m_axi_arlen(m_axi_arlen), // output wire [7 : 0] m_axi_arlen
.m_axi_arsize(m_axi_arsize), // output wire [2 : 0] m_axi_arsize
.m_axi_arburst(m_axi_arburst), // output wire [1 : 0] m_axi_arburst
.m_axi_arlock(m_axi_arlock), // output wire [0 : 0] m_axi_arlock
.m_axi_arcache(m_axi_arcache), // output wire [3 : 0] m_axi_arcache
.m_axi_arprot(m_axi_arprot), // output wire [2 : 0] m_axi_arprot
.m_axi_arregion(m_axi_arregion), // output wire [3 : 0] m_axi_arregion
.m_axi_arqos(m_axi_arqos), // output wire [3 : 0] m_axi_arqos
.m_axi_aruser(m_axi_aruser), // output wire [2 : 0] m_axi_aruser
.m_axi_arvalid(m_axi_arvalid), // output wire m_axi_arvalid
.m_axi_arready(m_axi_arready), // input wire m_axi_arready
.m_axi_rdata(m_axi_rdata), // input wire [63 : 0] m_axi_rdata
.m_axi_rresp(m_axi_rresp), // input wire [1 : 0] m_axi_rresp
.m_axi_rlast(m_axi_rlast), // input wire m_axi_rlast
.m_axi_ruser(m_axi_ruser), // input wire [2 : 0] m_axi_ruser
.m_axi_rvalid(m_axi_rvalid), // input wire m_axi_rvalid
.m_axi_rready(m_axi_rready) // output wire m_axi_rready
);

 

```

 

It seems like it can't find the module when I do a post-synthesis simulation.  I am trying to keep the VIP in the testbench and synthesize the component it is attached to.  I may have the setting wrong.  Any help would be appreciated.  

 

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