Post Synthesis Simulation with VIP in testbench Not Working Vivado 2017.1 Linux
I am using Vivdao 2017.1 on linux. I can get the behavioral simulation to work. However, when I try to do a post synthesis simulation I get the following error:
Using 8 slave threads. Starting static elaboration ERROR: [VRFC 10-2063] Module <axi_vip_0> not found while processing module instance <axi_vip_0_tb_inst> [/home/scratch.jclemons_nvresearch/hls/jclemons-research-scratch-hls/avr/sandbox_rc17/fpga/fpga_host/vivado/Jason_fpga_host_test_sim/Jason_fpga_host_test_sim.srcs/sim_2/new/testbench_postsyn.sv:401] ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed. INFO: [USF-XSim-69] 'elaborate' step finished in '5' seconds
It seems like it can't find the module when I do a post-synthesis simulation. I am trying to keep the VIP in the testbench and synthesize the component it is attached to. I may have the setting wrong. Any help would be appreciated.