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Visitor pimovietc
Registered: ‎11-29-2018

Post-Synthesis Timing Simulation incorrect

Hi all,


Currently I'm struggeling with a piece of code that has incorrect behavior during timing simulation and I fail to see why it is happening. I've even chosen an exteremely slow clock (period 100ns) to make sure it has nothing to do with timing constraints not being met.

I've identified the following bit as the culprit. By inspecting the waveforms I can see that paint_in always has the correct value (a 10 bit integer) and that for some reason paint_full (which is a flat array of 10-bit values) contains some glitches. Most values are 'copied' correctly, but some of them have random values, completely unrelated to paint_in.

always@(posedge clk) begin
    if (rst) begin
        paint_full  = 1'b0;
        RDY         = 1'b0;
        i           = 1'b0;    
    end else begin
        i = i + 1;
        if (i < LENGTH+1) begin
            paint_full[(i-1)*10 +: 10] = paint_in;
        end else if (i==LENGTH+1) begin
            RDY = 1'b1;

Does anyone have a clue what might be going on?

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Visitor pimovietc
Registered: ‎11-29-2018

Re: Post-Synthesis Timing Simulation incorrect

I've been building a small test module to see if I can further isolate the issue. Within this test module it hit me, I never changed the clk generated in the tb.In my test module I was having the same issue as before, everything is fine except the timing simulation. This is when I realised I was doing the simulation at a faster clk than I had in my constraints. So if anyone runs in to the same issue, first check that your clks match ;)

Whilst debugging in my original project I kind of broke it and can't quickly test if adjusting the simulation clk indeed fixes it. So in the mean time my question stands if there is any funny business with the above code. I'll update when I've come round to fixing the initial module.
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