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Visitor
Visitor
4,863 Views
Registered: ‎01-28-2009

Post-Translate Debug Methodology?

Hello all,

 

I'm looking for some high level guidance here. I'm using ISE 10.1 and Modelsim SE 6.4c. (iSim has a crash-bug on my design so Modelsim is a work-around).

 

I've got a medium size design (18% of an XC3S1200E) that passes a simple behavior simulation and which also compiles properly. When I try to run a post-translate simulation it fails. I've got the problem narrowed down, but I'm finding debugging this post-synth netlist to be such pain that I have to believe there is a better way. At the moment I have traced the problem to a particular LUT but I am having a lot of trouble understanding what that corresponds to in my source, so I'm having trouble tracing it back to a root cause.

 

Identify looks like a good tool and if it does what it says it does I think that would be very helpful, but it seems strange to me that all I'm really looking for easier way to understand the mapping of source HDL to post-translate logic and that using a hardware based solution (as opposed to simulation) might be the most direct solution to the problem.

 

Any input or ideas would be welcome.

 

Drew

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Xilinx Employee
Xilinx Employee
4,847 Views
Registered: ‎08-15-2007

Re: Post-Translate Debug Methodology?

Drew,

 

Refer to this thread to maintain hierarchy in the Post-Translate netlist.  Doing so should help you pin-point the relevant submodule in your design which you should concentrate on. 

 

Hope it helps.

Eddie
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Visitor
Visitor
4,828 Views
Registered: ‎01-28-2009

Re: Post-Translate Debug Methodology?

Thanks for the reply.

 

Yes, I've been trying to stop flattening of the design. I think it not be a complete solution to my problems, but it will help.

 

The thread you pointed out was helpful, but I still have not been able to prevent my hierarchy from being flattened. Item 2 was a little confusing - "checked off" - is that checked (on) or off? I assume checked, but I've tried it both ways. No luck, the design still gets flattened.

 

Drew

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Xilinx Employee
Xilinx Employee
4,773 Views
Registered: ‎08-15-2007

Re: Post-Translate Debug Methodology?

Drew,

 

Item 2 should be "checked off / unchecked" as we are asking Map to stop performing hierarchical optimizations (which can break hierarchical boundaries). However, since you are doing a Post-Translate simulation, options in Map are irrelevant.

 

I'm interested to learn if synthesis is indeed not honoring your request to maintain hierarchy.  You can use the Technology Viewer (under XST process) to view the netlist in schematic form.  Do so for when generating the netlist while using "Keep HIerarchy=false" vs "Keep Hierarch = Yes".  You should be able to see a difference (you can now "push" into the submodules)

 

If this is not ocurring, consider opening a WebCase to have a Product Applications Engineer help you out.

 

 

Eddie
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